Service manual

Schematic Diagrams
Processor 2/7 B - 5
B.Schematic Diagrams
Processor 2/7
SM _D RAM RS T#
IN3 .3 V
??IBEX CONTROL
R 247 *0_04
H_CPURST#
DDR3 Compensation Signals
H_ PR OC HO T# _ D
Processor Pullups
XD P _ T D I _ M
XDP _TR ST#
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
XD P _ T D O _ R
H_COMP2
H_COMP3
H_COMP1
H_COMP0
TRACE WIDTH 10MIL, LENGTH <500MILS
XDP _TM S
Intel change
4.75K -->1.1K
12K -->3K
DR AMP W RG D_ C PU
R 241 *10mil_short
R62
3K_1% _04
C3 1 8
*47n_50V_04
R 243 *51_04
R216 49.9_1%_04
R 54 10K_04
R245 * 68_04
R 239 *51_04
R234 20_1%_04
R202
* 100K_04
R50
1.1K_1%_04
R232 *8.2K_04
R6 1
750_1% _04
R 231 *12.4K_1%_04
R226 100_1%_04
R 240 *51_04
U1 7
*M C74VH C1G08DFT1G
1
2
5
4
3
R212 49.9_1%_04
R227 24.9_1% _04
R 249 *51_04
Q15
* RJU 003N03T106
G
DS
R 248 *10m il_short
R 250 *51_04
R244 *1.5K_1%_04
R 230 10K_04
CLOCKS
MISC THERMAL PWR MANAGEMENT
DDR3 MISC
JTAG & BPM
U16B
PZ98927-3641- 01F
SM_ R CO MP[1]
AM 1
SM_ R CO MP[2]
AN 1
SM_D RAM RST#
F6
SM_ R CO MP[0]
AL1
BCLK#
B16
BCLK
A16
B C LK _I T P #
AT3 0
BCLK_ITP
AR 30
PE G_CLK#
D16
PEG _CLK
E16
D PLL_R EF_SSCLK#
A17
DP LL_REF _S SCLK
A18
CA TER R#
AK14
CO MP 3
AT23
PEC I
AT15
PR OC HOT#
AN26
THER MTR IP#
AK15
RE SET_O BS#
AP26
VC CP W R GO OD _ 1
AN14
VC CP W R GO OD _ 0
AN27
SM _D RAM PW R OK
AK13
VTTPWRGOOD
AM15
RS TIN #
AL14
PM_ EXT_TS# [0]
AN 15
PM_ EXT_TS# [1]
AP 15
PRD Y#
AT2 8
PR EQ#
AP 27
TC K
AN 28
TM S
AP 28
TRST#
AT2 7
TD I
AT2 9
TD O
AR 27
TD I_M
AR 29
TDO _M
AP 29
DBR#
AN 25
BPM#[0]
AJ 2 2
BPM#[1]
AK 22
BPM#[2]
AK 24
BPM#[3]
AJ 2 4
BPM#[4]
AJ 2 5
BPM#[5]
AH 22
BPM#[6]
AK 23
BPM#[7]
AH 23
CO MP 2
AT24
PM _SY NC
AL15
TAPPW R GO OD
AM26
CO MP 1
G1 6
CO MP 0
AT26
SKTOC C#
AH24
R 238 51_04
R 52 * 10m il_short
R236 49.9_1%_04
R233 20_1%_04
R 60 1.5K_1%_04
R200
*1K _04
R228 130_1%_04
R237 68_04
R 242 51_04
1.1VS_ VTT
1.1VS_ VTT
1.5VS_CP U
1.1VS_VTT
3.3V
1.5V
BC LK_C PU _P 19
C LK _D P_P 15
C LK _D P_N 15
H_CPUPWRGD19
PM _DRA M_PW R GD16
H_VTTPWRGD16
BC LK_C PU _N 19
C LK _EXP_N 15
C LK _EXP_P 15
BUF _PL T_RST#18,23,25,28
PM_EXTTS# _EC 3
TS#_D IMM 0_1 10,11
H_THRMTRIP#19
H_PM_SYNC16
H _PECI19,28
1.1VS_VTT 2,6,7,14,15,16,19,20, 21,34,35,36
DR AMR ST_C T RL 9 ,1 9
DD R3_DR AMR ST# 10,11
1.5V 9, 10,11,21,23,27,29,31,33,36
D ELAY_ PW RGD16,36
PM_EXTTS#[ 0]
1.5VS_C PU 7,31
1.1VS_VTT_PW RG D 16,33,34
3.3V 3, 12,14,15,16,18,19,20,21,23,24,25,29,30, 31,33,34,35
H_ PR OC HO T#36
H_PROCHOT#_D
R 201 0_04
R229 *0_04
R53 *0_04
XDP _TD O_R
XD P _ T D O _ M
H_ CP UR ST#
R246 0_04
Processor Compensation
Signals
H_ PW R GD _XD P
PLT_ R ST#_R
XD P_PR EQ#
XD P _ T C L K
XD P_TRST#
XD P _ T M S
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
H_ CO MP 3
SYS_AG ENT_PW R OK
H_ CO MP 2
PM_EXTTS#[ 1]
H_ CO MP 1
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
SM_D RAM RST#
SM_R CO MP_0
XDP _TD O_M
XDP _TD I_R
SM_R CO MP_1
PROCESSOR 2/7 ( CLK,MISC,JTAG )
VDD P W R GO OD _R
SM_R CO MP_2
H_ CA TER R#
XDP_PREQ#
XDP _TC LK
XD P _ T D I _ R
H_ CO MP 0
XD P _ T D I _ M
BSS138 ( VGS 1.5V )
XDP _TD O_M
SM _R CO MP_ 2
SM _R CO MP_ 1
SM _R CO MP_ 0
VD DPW RG OO D_R
H_CATERR#
Sheet 4 of 40
Processor 2/7