Service manual

Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG) B - 5
B.Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
H_CP UR ST#
H_CO MP 2
H_CO MP 3
H_CO MP 1
H_CO MP 0
P M_EXTTS#[0]
H_PR OC HO T#_ D
XD P_TD O_M
H_ C PUR ST #
H_ PW RG D_ XDP
PLT_R ST#_R
XD P_PREQ #
XD P_TC L K
XD P_TR ST#
XD P_TM S
H_ C OM P3
SY S_AGEN T_ PW RO K
H_ C OM P2
P M_EXTTS#[1]
H_ C OM P1
SM_DRAMRST#
S M_RC OM P_0
XD P _ T D O _ M
XD P _ T D I _ R
S M_RC OM P_1
VD DP W R GO OD _ R
S M_RC OM P_2
H_ C ATERR #
XD P_PRE Q#
XD P _ T C L K
XD P_TD I_R
H_ C OM P0
XD P_TD I_M
XD P _ T M S
SM _R CO MP_ 2
SM _R CO MP_ 1
SM _R CO MP_ 0
XD P _ T D O _ M
H_ PRO CH OT# _ D
XD P_TRST#
SM_DR AMR ST#
XD P _ T D O _ R
XD P_TD O_R
XDP_TDI_M
DRAMPWRGD_CPU
R242 *51_04
IN 3 .3V
R251 *51_04
R2 4 9 * 0 _0 4
R 237 20_1%_04
R250 *10m il_short_04
C3 1 1
*47n_50V_04
R 236 20_1%_04
R229 100_1%_04
R5 3 *0 _04
R207
*100K _1%_04
CLOCKS
MISC THERMAL PWR MANAGEMENT
DDR3 MISC
JTAG & BPM
U16B
PZ 98927-3641-01F
SM_RC OM P[1]
AM 1
SM_RC OM P[2]
AN 1
SM_D RAM RST#
F6
SM_RC OM P[0]
AL1
BCLK#
B16
BC LK
A16
BCLK_ITP#
AT3 0
BCLK_ITP
AR 30
PEG _ CLK#
D16
PEG _C L K
E16
D P LL _ R E F _S S C L K #
A17
DPLL_REF_SSC LK
A18
CATERR#
AK14
COMP3
AT23
PEC I
AT15
PR OC HO T#
AN26
THER MTR IP#
AK15
R ESET_O BS#
AP26
VC CP W R GO OD _ 1
AN14
VC CP W R GO OD _ 0
AN27
SM _D RA MPW R OK
AK13
VT T P W R GOO D
AM15
RSTIN#
AL14
PM_EXT_TS#[0]
AN 15
PM_EXT_TS#[1]
AP15
PRDY#
AT2 8
PRE Q#
AP27
TC K
AN 28
TM S
AP28
TRST#
AT2 7
TD I
AT2 9
TDO
AR 27
TDI _M
AR 29
TDO _M
AP29
DB R#
AN 25
BPM#[0]
AJ 22
BPM#[1]
AK22
BPM#[2]
AK24
BPM#[3]
AJ 24
BPM#[4]
AJ 25
BPM#[5]
AH 22
BPM#[6]
AK23
BPM#[7]
AH 23
COMP2
AT24
PM _S YN C
AL15
TAPPW R GO OD
AM26
COMP1
G1 6
COMP0
AT26
SKTO CC #
AH24
R252 *51_04
R54 10K_04
R235 *8.2K_04
R2 3 0 24 .9 _1 % _ 0 4
R245 *51_04
R203
* 1K_1%_04
R2 4 4 51 _ 0 4
R 247 *68_04
R52 *10m il_short_04
R233 10K_04
R60 1.5K_1%_04
R206 *10m il_short_04
R243 *10m il_short_04
R2 3 2 *0 _0 4
R248 *10m il_short_04
R 213 49.9_1%_04
R231 130_1%_04
R61
750_1%_04
Q1 3
*R JU003N 03T106
G
DS
U17
*MC74VHC1G08DFT1G
1
2
5
4
3
R241 *51_04
R6 2
3K_1% _04
R234 *12. 4K_1%_04
R2 4 0 51 _ 0 4
R5 0
1.1K_1% _04
R246 *1.5K_1%_04
R 219 49.9_1%_04
R 239 68_04
R 238 49.9_1%_04
1.1VS_VTT
1.1VS_ VTT
1.1VS_ VTT
H_CPUPWRGD19
3. 3 V
1. 5 V
1.5VS_CPU
H_VTTPWRGD16
BCLK_CP U_N 19
BCLK_CP U_P 19
CLK_ DP_P 15
CLK_DP_N 15
TS#_D IMM 0_1 10,11
H_THR MTR IP#19
CLK_EXP_ N 15
CLK_EXP_ P 1 5
B UF_PLT_R ST#18,23,25,28
PM_D RAM _ PW RG D16
DELAY_PWRGD16,36
H_PM _ SYN C16
H_PEC I19 , 2 8
1.1V S_V TT 2,6,7,14,15,16, 19,20,21,34,35, 36
PM _EXTTS# _E C 3
1.1VS_VTT_P WRG D 16,33,34
3.3V 3,12,14,15,16,18,19,20,21,23,24,25,29,30,31,33,34,35
DRAMRST_CTRL 9,19
DD R3_DR AM RST# 10,11
1.5V 9,10,11,21,23,27,29,31,33,36
DDR3 Compensation Signals
P ro ce s so r Co mp en sa t io n
Signals
P ro ce s so r Pu ll up s
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
PROCESSOR 2/7 ( CLK,MISC,JTAG )
H_ PRO CH OT#36
1.5V S_C PU 7,31
BSS138 ( VGS 1.5V )
?? IBEX CONTROL
Intel change
4.75K -->1.1K
12K -->3K
TRACE WIDTH 10MIL, LENGTH <500MILS
VD DP W R GO OD _ R
H_CA TER R#
Sheet 4 of 42
CPU 2/7
(CLK, MISC, JTAG)