Service manual

Schematic Diagrams
B - 4 CPU 1/7 (DMI, PEG, FDI)
B.Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI)
Sheet 3 of 42
CPU 1/7
(DMI, PEG, FDI)
PLACE NEAR U16
3
2
1
PEG_IR CO MP_R
EXP _R BIAS
D1 6 *C DBU 0 03 4 0
AC
Analog Thermal Sensor
20 mil
C3 6 0
0. 1u _ 1 6V _Y 5 V _ 04
R208 750_1% _04
Q10
*2N3904
B
E C
C357
*0.1u_16V_Y5V_04
C359
0.1u_16V_Y 5V _04
Q14
G7 1 1 ST9 U
OU T
1
VCC
2
GN D
3
R209 49.9_1%_04
1:2 (4mils:8mils)
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
U16A
PZ98927-3641-01F
DM I_RX# [0 ]
A24
DM I_RX# [1 ]
C23
DM I_RX# [2 ]
B22
DM I_RX# [3 ]
A21
DM I_RX[0 ]
B24
DM I_RX[1 ]
D23
DM I_RX[2 ]
B23
DM I_RX[3 ]
A22
DM I_TX#[0]
D24
DM I_TX#[1]
G2 4
DM I_TX#[2]
F23
DM I_TX#[3]
H23
DM I_ TX[0 ]
D25
DM I_ TX[1 ]
F24
DM I_ TX[3 ]
G2 3
DM I_ TX[2 ]
E23
FD I_TX#[0]
E22
FD I_TX#[1]
D21
FD I_TX#[2]
D19
FD I_TX#[3]
D18
FD I_TX#[4]
G2 1
FD I_TX#[5]
E19
FD I_TX#[6]
F21
FD I_TX#[7]
G1 8
FD I_TX[0 ]
D22
FD I_TX[1 ]
C21
FD I_TX[2 ]
D20
FD I_TX[3 ]
C18
FD I_TX[4 ]
G2 2
FD I_TX[5 ]
E20
FD I_TX[6 ]
F20
FD I_TX[7 ]
G1 9
FD I_F SYN C[0]
F17
FD I_F SYN C[1]
E17
FD I_IN T
C17
FD I_LSY NC [0]
F18
FD I_LSY NC [1]
D17
PEG_IC OM PI
B26
PEG _ICO MPO
A26
PE G_ RBI AS
A25
PEG_R CO MPO
B27
PE G_ RX# [0]
K35
PE G_ RX# [1]
J34
PE G_ RX# [2]
J33
PE G_ RX# [3]
G35
PE G_ RX# [4]
G32
PE G_ RX# [5]
F34
PE G_ RX# [6]
F31
PE G_ RX# [7]
D35
PE G_ RX# [8]
E33
PE G_ RX# [9]
C33
PEG_R X#[10 ]
D32
PEG_R X#[11 ]
B32
PEG_R X#[12 ]
C31
PEG_R X#[13 ]
B28
PEG_R X#[14 ]
B30
PEG_R X#[15 ]
A31
PEG _RX[0]
J35
PEG _RX[1]
H34
PEG _RX[2]
H33
PEG _RX[3]
F35
PEG _RX[4]
G33
PEG _RX[5]
E34
PEG _RX[6]
F32
PEG _RX[7]
D34
PEG _RX[8]
F33
PEG _RX[9]
B33
PE G_ RX[10 ]
D31
PE G_ RX[11 ]
A32
PE G_ RX[12 ]
C30
PE G_ RX[13 ]
A28
PE G_ RX[14 ]
B29
PE G_ RX[15 ]
A30
PEG _ TX#[0]
L33
PEG _ TX#[1]
M35
PEG _ TX#[2]
M33
PEG _ TX#[3]
M30
PEG _ TX#[4]
L31
PEG _ TX#[5]
K32
PEG _ TX#[6]
M29
PEG _ TX#[7]
J31
PEG _ TX#[8]
K29
PEG _ TX#[9]
H30
PE G_ T X#[10 ]
H29
PE G_ T X#[11 ]
F29
PE G_ T X#[12 ]
E28
PE G_ T X#[13 ]
D29
PE G_ T X#[14 ]
D27
PE G_ T X#[15 ]
C26
PEG _TX[0]
L34
PEG _TX[1]
M34
PEG _TX[2]
M32
PEG _TX[3]
L30
PEG _TX[4]
M31
PEG _TX[5]
K31
PEG _TX[6]
M28
PEG _TX[7]
H31
PEG _TX[8]
K28
PEG _TX[9]
G30
PEG _ TX[10]
G29
PEG _ TX[11]
F28
PEG _ TX[12]
E27
PEG _ TX[13]
D28
PEG _ TX[14]
C27
PEG _ TX[15]
C25
U1 8
*W83L771AWG
VDD
1
D+
2
D-
3
THE RM
4
GN D
5
ALER T
6
SDA TA
7
SC LK
8
R 22 8 * 1 0m i l _s h o r t _ 0 4
3.3V
3.3V
DM I_TXP116
DM I_TXP016
DM I_TXN016
DM I_TXP316
DM I_TXP216
DM I_TXN316
DM I_TXN216
DM I_TXN116
DMI_RXN216
DMI_RXN116
DMI_RXN016
DMI_RXP116
DMI_RXP016
DMI_RXN316
FDI_FSY NC 116
FDI_FSY NC 016
DMI_RXP316
DMI_RXP216
FDI_LSYN C116
FDI_LSYN C016
FDI_ IN T16
FD I_TXN 216
FD I_TXN 116
FD I_TXN 016
FD I_TXN 516
FD I_TXN 416
FD I_TXN 316
FD I_TXP016
FD I_TXN 716
FD I_TXN 616
FD I_TXP416
FD I_TXP316
FD I_TXP216
FD I_TXP116
FD I_TXP716
FD I_TXP616
FD I_TXP516
SM C_ CPU _ T HER M 15 ,2 8
3. 3 V4 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9 ,20 ,2 1 ,2 3,2 4 ,2 5 ,2 9,30 ,3 1 ,33 ,3 4 ,3 5
PM _EXTTS# _ EC 4
THER M_ ALER T# 28
SM D_ CPU _ T HER M 15 ,2 8
CRIT_TEMP_REP# 19
THER M_VO LT 28
Thermal Sensor near U16
PROCESSOR 1/7 ( DMI,PEG,FDI )
It applies to Auburndale and Clarksfield discrete graphic designs.
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected
to GND if motherboard only supports discrete graphics and also in a common
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed,
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from
floating).
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] ca
n be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale.
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common
motherboard design case. Please not that if these signals are left floating, there are no
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on
Auburndale can be left as no connect.
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale
directly if motherboard only supports discrete graphics. In a common motherboard
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no
external termination is required.