Service manual

Schematic Diagrams
Clock Generator B - 3
B.Schematic Diagrams
Clock Generator
CLOCK GENERATOR
100MHz100MHz1(0.7V-1.5V)
0(default)
PIN_30 CPU_1CPU_0
133MHz133MHz
R137 10K_04
CPU_SEL_During CK_PEWGD Latch Pinl
CLK_ SDATA
CLK_ SCL K
CLK_PW RG D
SMBus
CLK_ SDATA
CLK_ SCL K
3.3VS
SMB_ DATA15
SMB_ CLK15
CLK_SDATA 10 ,11
CLK_SCLK 10,11
L15 * 15m il_short_06
L14 *15mil_short_06
3.3V 3,4,12,14,15,16,18,19,20,21,23,24,25,29,30, 31,33,34,35
REF _ 0 /CPU_ SEL
5VS
S D
G
Q1 1A
MT DN 70 0 2Z H S 6 R
2
6 1
S D
G
Q1 1B
MT DN 70 0 2Z H S 6 R
5
3 4
RE F_0 /CPU _ SEL
0.1uF near the every power pin
CLKGEN POWER
0.1uF near the every power pin
VDD_I/O can be
ranging from
1.05V to 3.3V
5VS 13,17,20,21,26,27,30,31,35,36
EMI Capactior
EMI
XIN
Slego SLG8SP585 6-02-08585-EQ0
Realtek RTM875N-632-VB-GRT
C20 5
0.1u_16V_Y5V_04
R149
10K_1%_04
C2 07
1u_6.3V_X5R _04
X1 HSX530G_14.31818M Hz
12
C1 99
33p_50V_NPO_04
R146
1M_04
C202
33p_50V_N PO_04
Q1 2
MT N7 00 2 ZHS3
G
DS
C2 06
0.1u_16V_Y5V_04
C1 9 6
1u_6.3V_X5R_04
C197
0.1u_16V_Y 5V_04
CPU _S T O P#
REF_0/CPU_SEL C 194 *10p_50V _N PO_06
U7
SLG 8SP585
VD D_DO T
1
VD D_2 7
5
VD D_SRC
17
VD D_CPU
24
VD D_REF
29
VSS _D OT
2
XTAL_O UT
27
XTAL_IN
28
R EF_ 0/C PU_SEL
30
SD A
31
SC L
32
VSS _27
8
VSS _SATA
9
VSS _SR C
12
VSS _C PU
21
VSS _R EF
26
V DD_ SR C_ I/O
15
V DD_ CP U_ I/O
18
DOT_96
3
DO T_9 6#
4
27M
6
27M_SS
7
SRC _1/SATA
10
S RC_1 #/S ATA#
11
SRC _2
13
SR C_2#
14
CPU_ STOP#
16
CPU _1
20
CP U_ 1#
19
CPU _0
23
CP U_ 0#
22
CK PW RGD /PD#
25
GND
33
3.3VS
CL K_ VCC 2CLK_VCC 1
CLK_VCC2
3.3VS
CLK_ VCC1
1.1VS_V TT
3.3VS
3.3VS
CLK_BUF_DOT96_N 15
CLK_ BUF_R EF1415
CLK_BUF_DOT96_P 15
CLK_BUF_BCLK_N 15
CLK_BUF_BCLK_P 15
1.1VS_VTT 4,6,7,14,15,16,19, 20,21,34,35,36
3.3VS 10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,35,36
CLK_SATA 15
CLK_PCIE_ICH# 15
C LK _PC IE_ICH 15
CL KEN #36
CLK_SATA# 15
XO U T
XI N
R134 33_04
RN 15
2.2K_4P2R_04
1 4
2 3
R 1 48 2. 2 1 K _ 1 % _ 04
6-22-14R31-1B7
6-22-14R31-1B6
XOUT
R136 *4.7K_04
Sheet 2 of 42
Clock Generator