Service manual

Schematic Diagrams
B - 12 Mainboard (71-D6100-D03)
Schematic Diagrams
650-3 (HyperZip/VGA/Misc) - 3 of 4
Sheet 10 of 30
650-3
(HyperZip/VGA/Misc)
3 of 4
+5VS
+3VS
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+1.8VS +1.8VS+1.8VS
+5VS +5VS
+3VS
+3VS
+5VS +5VS
INTA# [12,14]
ZAD[0..15][14]
ZSTB[0..1][14]
ZSTB-[0..1][14]
PCIRST#[12,14,18,19,20,21,22,23,28]
PWRGD[13,15,28]
REFCLK0
[5]
ZCLK0
[5]
FRED[16]
FGRN [16]
FBLU [16]
DDCDA [16]
HS [16]
VS [16]DDCDC[16]
ZUREQ
[14]
ZDREQ
[14]
AUXOK [4,15,23,26]
REFCLK0
ROUT
GOUT
BOUT
Z0801 HSYNC
Z0802 VSYNC
DDC1CLK
DDC1DATA
INTA#
Z1XAVDD
DDC1DATA
CSYNC
RSYNC
LSYNC
ZSTB[0..1]
ZSTB-[0..1]
ZAD[0..15]
RSYNC PWRGD
AUXOK
ENTEST
FGRN
ROUT
FBLU
FRED
Z0804
Z0803
Z0805
HSYNC
VS
DDC1CLK
GOUT
ZAD10
ZSTB0
ZAD12
ZAD6
ZSTB-0
ZAD8
ZSTB-1
ZCMP_P
ZAD15
ZCLK0
ZAD14
ZAD9
ZAD1
ZAD0
ZUREQ
ZDREQ
ZAD7
ZVREF
ZAD2
ZAD13
ZAD11
ZAD5
ZAD3
ZSTB1
ZAD4
BOUT
HS
DDCDC
TRAP1
TRAP0
TMODE2
TMODE1
TMODE0
DLLEN-
ENTEST
ECLKAVSS
ECLKAVDD
DCLKAVDD
VVBWN
DACAVSS
VRSET
DACAVDD
VCOMP
FGRN
FRED
FBLU
DDCDA
VS
HS
DDCDC
ROUT GOUTBOUT
HSDDCDC VS
Z0803
VSYNC
Z1XAVSS
Z4XAVSS
Z4XAVDD
DDCDA
DDCDA
TZ0802
TZ0801
ZCMP_N
VDDZCMP
VSSZCMP
Z0803
Z0803
Z0803
T16
T15
T14
T13
T22
T21
T20
T19
T18
T17
R256 100
R259 100
R260
*4.7K
R258
*4.7K
L24
0(0805)
1 2
C371 0.1UF
C369 0.1UF
JVGA1
VGA DSUB
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
GND1
GND2
N4
N7
L32
FCM1608K-121T07
1 2
L33
FCM1608K-121T07
1 2
L31
FCM1608K-121T07
1 2
N5
L10
HCB1608K-121T25
1 2
L12
HCB1608K-121T25
1 2
N15
L11
HCB1608K-121T25
1 2
L27
FCM1608K-121T07
1 2
L28
FCM1608K-121T07
1 2
L25
FCM1608K-121T07
1 2
L26
FCM1608K-121T07
1 2
C74
10UF/16V
C77
0.1UF
D39 RB751V
AC
N14
L42
HCB1608K-121T25
1 2
L2
HCB1608K-121T25
1 2
L48
HCB1608K-121T25
1 2
C89
10UF/16V
C86
0.1UF
C78
0.1UF
C79
0.01UF
C90
0.1UF
C88
0.1UF
C87
0.01UF
C76
0.01UF
C374
220PF
C384
22PF
C385
22PF
C362
22PF
C361
22PF
C115 0.1UF
C114
0.1UF
C73
10UF/16V
C404
0.01UF
C399
0.1UF
C383
22PF
C363
22PF
C373
1000PF
C375
1000PF
C376
220PF
C403
0.1UF
C396
1UF
C82
10UF/16V
C391
0.1UF
C388
10UF/16V
C9
10UF/16V
C15
0.1UF
C17
0.01UF
R257
2.2K
R250
2.2K
R254
75
R253
75
R255
75
C18
0.1UF
R47
56
R9
4.7K
R39
56
R46
150 1%
R45
150 1%
R251
33
R249
33
C372
0.1UF
C377
0.1UF
D8
BAV99
C
AC
A
D7
BAV99
C
AC
A
R10
130 1%
R8 4.7K
U23C
SIS650
C15
A12
B13
A13
F13
E13
D13
D12
B11
E12
A11
F12
E14
D14
F14
B12
C12
C13
C14
B15
A15
B14
A14
F10
E11
C11
F11
A10
D11
E10
Y3
W4
W6
V2
V1
W1
W2
V5
U4
U2
V6
U3
T4
R3
T5
T6
R2
R6
R1
R4
P4
N3
P5
P6
N1
N6
N2
N4
P1
P3
T3
T1
U6
U1
V3
VOSCI
ROUT
GOUT
BOUT
HSYNC
VSYNC
VGPIO0
VGPIO1
INT#A
CSYNC
RSYNC
LSYNC
VCOMP
VRSET
VVBWN
DACAVDD1
DACAVSS1
DACAVDD2
DACAVSS2
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
ENTEST
DLLEN#
TESTMODE0
TESTMODE1
TESTMODE2
TRAP1
TRAP0
PCIRST#
PWROK
AUXOK
Z4XAVDD
Z4XAVSS
Z1XAVDD
Z1XAVSS
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
ZVREF
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZSTB1
ZSTB#1
ZSTB0
ZSTB#0
ZUREQ
ZDREQ
ZCLK
D5
BAV99
C
AC
A
D4
BAV99
C
AC
A
D3
BAV99
C
AC
A
D2
BAV99
C
AC
A
D6
BAV99
C
AC
A
650-3
VGA
HyperZip
DLLEN#
DRAM_SEL
TRAP0
TRAP1
SDR
LSYNC
CSYNC
RSYNC
1(DDR)
(30~50K Ohm)Default
DDR
0
1
0
embedded pull-low
0
0 yes
disable PLL
yes
1
NB debug mode
0
yes
0
normal
NOTE: This page is for universal PCB design( suitable for both 645 or 650)
NB Hardware Trap Table
enable panel link
enable VGA interface
enable PLL
TV selection, NTSC/PAL(0/1)
enable VB
NEAR SIS650
12
3
SOT-23
BAV99
AS SIS AP NOTE
A650-0-003
35.4mA
6.49mA
7.92mA
84.8mA
7.57mA
18.07mA
20MIL
10MIL
10MIL
10MIL
20MIL
10MIL