Service manual

Schematic Diagrams
CLOCK GENERATOR, CCD B - 19
B.Schematic Diagrams
CLOCK GENERATOR, CCD
VCC _CC D
VCC _CC D
3. 3 V M _ C L K
5V
3.3VM
3. 3V M _ C L K
3.3VM _C LK
CCD_EN22
3. 3V S2,3,5,9,12,13,14,15,16,19, 20,21,22,23,24,25,28,30,33,35,37
CLK_ C PU_ BC L K 2
CLK_ C PU_ BC L K# 2
U SB_PP814
USB_PN814
CC D_DET #22
CLK_PW R GD15
ICH _SMBD AT010 , 1 1 , 1 5
CLK_PC IE_ 3 GPLL# 5
CLK_PC IE_ 3 GPLL 5
CLK_SATA 13
CLK_SATA# 1 3
CLK_ M CH _B CL K# 4
CLK_ M CH _B CL K 4
CLK_PC IE_ MXM 37
CLK_PC IE_ MXM # 37
CLK_PC IE_ TV 36
CLK_PC IE_ TV# 36
CLK_ PC IE_ NEW _ C ARD 21
CLK_ PC IE_ NEW _ C ARD # 21
CLK_PC IE_ W LAN 36
CLK_PC IE_ W LAN# 3 6
CLK_PC IE_ GLAN # 19
CLK_PC IE_ GLAN 1 9
CLK_PC IE_ ICH 1 4
CLK_PC IE_ ICH # 14
CLK_D REF_SS 5
CLK_D REF_SS # 5
CLK_D REF 5
CLK_D REF# 5
ICH _SMBC LK010 , 1 1 , 1 5
PM_ STPC PU#15
PM _STP PCI#15
CLK_ICH4815
CPU_BSE L02,4
CPU_BSE L12,4
CPU_BSE L22,4
CLK_ICH1415
P C LK _K B C22
5V S12,13, 15,16,17,23,24,25,26,28,33,37,38
5V16,17,30,31,32,34,35,38
CLK_PC IE_ CR 20
CLK_PC IE_ CR # 20
CLK_PC IE_ RO BSO N 36
CLK_PC IE_ RO BSO N# 36
RO BSO N_CLKR EQ#36
TV _ C L K R E Q #36
NE W CAR D_C L KREQ # 2 1
WLAN _C LKREQ # 36
GLAN _CLKR EQ# 19
MXM _ CL K R E Q# 3 7
PCLK_IC H14
Z1840
Z18 41
CCD_EN
Z1839
CL K_ PC IE_ TV
CL K_ PC IE_ ICH #
C LK_CPU _BCLK#
CL K_ PC IE_ ICH
CLK_ M CH _BC LK#
PCLK_IC H
CL K_ SAT A#
CLK_ M CH _BC LK
C LK_P CIE_N EW _ CAR D
CL K_ PC IE_ GLAN #
CLK_PC IE_3G PLL#
C LK_P CIE_N EW _ CAR D#
CL K_ IC H4 8
CL K_ SAT A
CL K_ PC IE_ 3G PL L
XT A L _ I N
CL K_ PC IE_ GLAN
C LK_CPU _BCLK
CL K_ PC IE_ TV #
PCLK_KBC
CL K_ IC H1 4
CCD_DET#
CLK_ PC IE_ MXM#
CLK_ PC IE_ MXM
Z1838
C LK_PCIE_3G PLL#
C LK_PCIE_3G PLL
C LK_P CIE_R OBSO N
C LK_P CIE_R OBSO N#
CLK_PCIE_CR
CLK_PCIE_CR#
CLK_SATA#
CLK_SATA
C LK_MC H_ BC LK#
C LK_MC H_ BC LK
C LK_PCIE_M XM
C LK_PCIE_M XM#
C LK_PCIE_N EW _ CA RD
C LK_PCIE_N EW _ CA RD #
CLK_PCIE_GLAN#
CLK_PCIE_GLAN
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PW R GD _T
XT A L _ O U T
PM _STP CPU #
PM _STP PCI#
CLK_ICH48
FSLA
FSLB
CLK_ICH14
FSLC
PC LK_K BC
Z1802
Z1805
Z1804
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CL K_ D REF
CL K_ D REF#
CL K_ D REF_ SS
CLK_ D REF_SS#
Z1842
Z1843
Z1844
Z1806
RN 7
*4 P2 R X0 _ 0 4
1 4
2 3
C234 * 10p_NP O_04
R178 475_1%_04
C176 * 10p_NP O_04
C180 * 10p_NP O_04
RN 21
*4 P2 R X0 _ 0 4
14
23
C50 8
0.1u_16V_04
C181 * 10p_NP O_04
C225 * 10p_NP O_04
C235
0.1u_10V_04
R1 38 10 K_ 04
C222 * 10p_NP O_04
RN 13
*4 P2 R X0 _ 0 4
14
23
R1 72 10 K_ 04
C214 * 10p_NP O_04
C209 * 10p_NP O_04
R12
100K_04
X2
*1 4 .3 18 M Hz
12
C50 9
10U_10V _08
R 1 33 0 _ 04
RN 11
*4 P2 R X0 _ 0 4
14
23
C202
27p_NPO _04
RN 10
*4 P2 R X0 _ 0 4
14
23
C186
* 0. 1u_X7R _04
R158 12.1_1%_04
C201 * 10p_NP O_04
C233 * 10p_NP O_04
RN 20
*4 P2 R X0 _ 0 4
14
23
C177 * 10p_NP O_04
R672 22_04
RN 19
*4 P2 R X0 _ 0 4
14
23
R 1 7 7 2. 2K _ 0 4
R1 68 10 K_ 04
C267 * 10p_NP O_04
C269 * 10p_NP O_04
C268 * 10p_NP O_04
C270 * 10p_NP O_04
L17
H CB2012KF-500T40
C271 * 10p_NP O_04
R14
68K_06
C220 * 10p_NP O_04
L6 0 _0 8
1 2
RN 4
*4 P2 R X0 _ 0 4
1 4
2 3
C183 * 10p_NP O_04
C 20 1u_10V_06
C2 1 0
27 p _ N P O _ 0 4
C272 * 10p_NP O_04
Q4
2N 7002
G
DS
C21 6
0.1u_10V_04
RN 16
*4 P2 R X0 _ 0 4
14
23
U5
ICS 9LPR 3 95 yKL F T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
CK _PW RG D/PD #
CR #_A
GN DR EF
X2
X1
VD DR EF
CR #_B
RE F0/ F SL C
SD ATA
SC LK
PC I0/C R#_C
VDD PCI
PC I1/C R#_D
FSLB/PC I2
PC I3
PC I4/27_Select
PC I_F 5/ITP_EN
GNDPCI
CR #_E
VD D48
US B_48M Hz/ FSLA
GN D4 8
S RC T0_LPR/D OTT_96_LPR
SR CC 0_ LPR /DO TC_ 96_ L PR
VDD
27MHz_NonSS/SRCT1/LCD-SST_LPR
27MH z_ SS/SR CC 1/LCD -SSC_ L PR
GND
VDDSRC0
GN DSR C0
CR #_F
S A TA T_ L P R
SATAC_L PR
VDD A
GNDA
SRC T2 _ LPR/ CR #_ G
SRC C2_LPR/ CR #_H
SRC T3_L PR
SR CC 3_LPR
PC I_S TO P#
SRC T4_L PR
SR CC 4_LPR
SRC T5_L PR
SR CC 5_LPR
SR CC 6_LPR /CR #_I
SR CT6_LPR/C R#_J
GN DS RC 1
SRC T7_L PR
SR CC 7_LPR
SRC T8_L PR
SR CC 8_LPR
SRC T9_L PR
SR CC 9_LPR
VD DSR C1
SR CC 1 0_LPR
SR CT10_ L PR
GN DSR C2
S R C C 1 1 _L P R / C R # _K
S RC T11_LPR/C R#_L
CR #_M
SR CC 1 2_LPR
SR CT12_ L PR
CP UC 2_ITP/SR CC 1 3_L PR
C PUT2 _ ITP/SR CT 1 3_L PR
CP U_ STOP#
SEL27_SR C1/R ESET#
CPUC1_LPR_F
CPUT1_LPR_F
GNDCPU
CP UC 0_ LPR
CPU T0_ LPR
VDD CPU
GN D_ M
C179 * 10p_NP O_04
RN 18
*4 P2 R X0 _ 0 4
14
23
C2 5 4
0.1u_10V_04
C178 * 10p_NP O_04
C187
0. 1u _ 1 0V _0 4
C198
0.1u_10V_04
R1 66 10 K_ 04
R164 22_04
C26 4
10U_10V_08
C256
10 U _1 0 V _ 0 8
C25 1
1u_6.3V _04
C2 7 5
10U_10V _08
C241 * 10p_NP O_04
C252
1u_6.3V_04
C2 5 3
1u_6.3V_04
C26 5
0.1u_10V_04
R1 54 10 K_ 04
C2 6 6
0.1u_10V_04
R13 330K_04
C255
0. 1 u _ 1 0V _ 0 4
JC C D 1
CON5_M
1
2
3
4
5
C243 * 10p_NP O_04
R 134 10K_04
C239 * 10p_NP O_04
RN 6
*4 P2 R X0 _ 0 4
1 4
2 3
C218 * 10p_NP O_04
R176 33_04
Q3
AO 3409
G
DS
C273 * 10p_NP O_04
R174 *475_1%_04
R157 *475_1%_04
RN 15
*4 P2 R X0 _ 0 4
14
23
RN 3
*4 P2 R X0 _ 0 4
1 4
2 3
C182 * 10p_NP O_04
C246 * 10p_NP O_04
X3
14.318MH z
12
C247 * 10p_NP O_04
RN 5
*4 P2 R X0 _ 0 4
1 4
2 3
C194 * 10p_NP O_04
FROM H8 def HI
CLOCK GENERATOR
Layout note:
CCD
Layout note:
PLACE CRYSTAL WITHIN 500
MILS OF ICS9LPR363
Place terminationclose to
ICS9LPR395
JCCD
51
40 mil
SRC3 Card Reader (NO CR#)
SRC4 Robson
SR C5 TV
SR C7 New Ca rd
SR C8 WLA N
SR C9 GLAN
SR C10 I CH (NO CR #)
SR C12 MXM
SR C13 MCH _PEG (NO CR#)
1
27FIX/SS
Pin23
Pin24
Pi n2 6
Pi n2 7
SE L2 7
_S RC 1
(p in 66 )
0
1
SRC0
DOT96
1
0
SRC0
0
DOT96
SR C1
1
0
27_Select
(pin16)
LC DS S
SRC1
0
66 7 MH z
01
1
0
BS EL 2
0
0
Frequency
0
0
80 0 MH z
BS EL 1
1
BS EL 0
Host Clock
53 3 MH z
0
1
1066 MHz
EVT
2007/12/10
3/15_Cost down
Sheet 18 of 42
CLOCK
GENERATOR, CCD