Service manual
1
2
3
4
5
B
C
B
B – 13
CLOCK GENERATOR
REV. 2
FIG. B 12
clock
+3VS
+3V
+3V
+3VS
+2.5VS
+3VS
+3VS
+3V
+3V
+3V
+3V
+3VS
HCLK_CPU 2,7
HCLK_1 3
PCLK_BX 8
PCLK_AUDIO 25
PCLK_PCM 24
PCLK_PIIX4 15
14 . 3M _P X4 1 5
SUSA# 15
PCLK_IO 18
14.3M_IO 18
CLK_SDRAM0 12
CLK_SDRAM1 12
CLK_SDRAM3 12
CLK_SDRAM2 12
SDRAMCLK7 7
SDRAM_CLKIN7
SUSA#15
PCI_ST P#15
G_CPU-ST P#3
SCLK_A 12
INHIB15
SDAT A _B 12
DRAMENB15
SDAT A _A 12
PDAT_SMB4, 1 5
PCLK_SMB4,1 5
DRAMENA15
SCLK_B 12
CLK_48MHZ 15
R_CLK_SDRAM0
R_CLK_SDRAM1
R_CLK_SDRAM2
R_CLK_SDRAM3
PCLK_SMB
PDAT_SMB
CK BF V CC
GND
R_HCLK_CPU
R_14 .3M _P X4
R_ P C LK _M T S C
R_PCLK_PCM
R_CLK_48MHZ
R_PCLK_AUDIO
R_PCLK_IO
R_PCLK_PIIX4
SDAT A _A
PDAT_SMB
SCLK_A
SDAT A _B
PCLK_SMB
SCLK_B
GND
CLKVCC
R309
2M
R124
22
R122
10
R125
10
R127
10
R129
10
R128
47K
L2 0
HB-1H3216-700T 05
1 2
L7 0
BK1608LL121
1 2
T73
T80
T83
T79
T75
C176
.1UF
C151
1000PF
C149
.1UF
C159
.1UF
C160
.1UF
C175
.1UF
C437
10PF
C436
10PF
C150
10UF
C472
.1UF
C467
1000PF
C127
1000PF
C466
.1UF
C452
.1UF
C440
.1UF
C468
.1UF
U13
SDRAM-BUF
1
5
10
19
24
28
4
8
12
17
21
25
16
13
2
3
6
7
22
23
26
27
11
18
9
15
14
20
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSSIIC
VDDIIC
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
BUF_IN
SCLOCK
SDATA
OE
D26
RB751V
12
Y1
14 . 31 8M H z
1 2
R133
10
C172
10PF
R324 10K
L6 8
BK1608LL121
1 2
C444
.1UF
C455
.1UF
C443
.1UF
C451
8200PF
C453
10UF/16V
R320 *10K
R97 10K
R101 10K
R328 10K
R340 22
R342 10K
R326 33
R327 22
R323 33
R322
22
+
C435
10UF/16V
12
R318 33
R313 22
R335 33
R332 *0
R321 33
D9
RB751V
1 2
R139
10K
RP20
*8P4RX100K
8 1
7 2
6
5
3
4
C179
*.1UF
R142
10K
R135
*10K
U14
*HC4 052_T S S O P
6
10
9
13
3
12
14
15
11
1
5
2
4
16
8
7
INHIBIT
A
B
X
Y
X0
X1
X2
X3
Y0
Y1
Y2
Y3
VCC
GND
VEE
U36
W137H
2
3
17
20
24
23
4
5
26
10
11
13
27
6
9
15
21
22
1
7
14
18
16
25
8
12
19
28
X1
X2
PWR_DWN#
PCI_STO P#
CPUCLK0
CPUCLK1
PCICLK _F
PCICLK1
REF1/SPREAD#
PCICLK4
PCICLK5
48 M HZ
REFO/SEL48#
PCICLK2
PCICLK3
GND
GND
GND
GND
GND
24/48MHz/OE
CPU_ST O P#
SEL_100/66#
VDDQ2
VDDQ3
VDDQ3
VDDQ3
VDDQ3
R105 10K
C155
*15P
T203
CLOCK GENERATOR
CLK lines roubting guide
HCLK_CPU: The trace width from CK66 to juntion that 10mils width is required.
5 mil trace width from junction branch to CPU and 440BX are required.
The length from CK66 to CPU = CK66 to 440BX + 1500 mils
PCLK_MTXC:
PCLK_MTXC = HCLK_CPU( from CK66 to 440BX).
SDRAMCLK :
Maximum length < 4inches
R124,C155 NEAR TO U10