Service manual

PN 4237242C
2.4-3
INSTRUMENT DESCRIPTION
SYSTEM CONTROL
2
Keypad Controller
The heart of the keypad controller is an 8279 keyboard controller chip. This chip is operated
in "scan keyboard" mode. The keypad is a standard row and column matrix, and with the
help of an HC138 decoder used to decode the rows, the keypad controller is able to sense any
pressed keys. Communication with the keypad is through J5 (Figure 2.4-2), a 20-pin in-line
connector that receives the flex cable connector from the keypad.
Display Controller
The display controller is made up of a connector for the display, an 8-bit buffer, a
programmable logic device or GAL, and a Display Contrast circuit. The connector, J4
(Figure 2.4-2), provides the display with its data bus, command functions, power and a
contrast setting. Data is provided directly from the CPU. The GAL provides each of the eight
display command functions its own port, enabling the CPU to control the display. Two
voltages are provided for the display, +5 V for power and a variable supply to control display
contrast. Display contrast can be adjusted with R5.
The display control logic (GAL) provides support for the options switch function. By
addressing a GAL port, the CPU can read the eight-position options switch, providing a
read-only port with up to 256-coded combinations.
CMOS RAM
The URA card provides a single chip of CMOS static RAM (Figure 2.4-2). This RAM chip has
an internal battery and power management circuitry, making it non-volatile. A programmable
logic GAL is used to control this chip.
The instrument uses this memory to store all user system settings, like aperture current
voltages, print formats, calibration factors and host interface settings. The data in RAM is
actually an image of a file on the Program Disk named PD.DAT. A new Program Disk contains
default settings and if there is no data in memory, the PD.DAT file is stored in the RAM.
It is important to understand how the instrument’s software deals with these two sources of
user information, especially during power up. When the instrument software first begins
executing after loading from diskette, it strives to establish a good and uniform system of user
settings. To do this, six pieces of information are obtained.
1. The CMOS image is verified using a CRC algorithm.
2. The CMOS image’s version is checked against the loaded software version.
3. The PD.DAT file is verified using a CRC algorithm.
4. The PD.DAT file’s version is checked against the loaded software version.
5. The diskette is checked to see if it can be written to.
6. The PD.DAT file is compared to the CMOS image to see if they match.
An error is generated if:
r Both files are bad, whether they are an old version or failed the CRC.
r PD.DAT is old or failed CRC and the diskette cannot be written to.
r PD.DAT has different settings but the diskette cannot be written to.
The CMOS RAM image is copied to PD.DAT if:
r PD.DAT failed CRC.
r PD.DAT is an old version.
r PD.DAT has different settings than the CMOS RAM image.
PD.DAT is copied to CMOS RAM if:
r The RAM image failed CRC.
r The RAM image is an old version.