Datasheet

Cisco UCS B250 M2 Blade Server

CONFIGURING the SERVER

(4) 2-CPU Configuration with Memory Mirroring

■ 32 DIMMs capacity total

■ Select 2, 4, or 8 DIMM kits (4, 8, or 16 DIMMs) per CPU. The DIMMs will be placed by the

factory as shown in the following table:

■ Choose the memory mirroring option (N01-MMIRROR) as shown in Table 4 on page 11.

Caveats

■ Only Cisco memory is supported. Third party DIMMs are not tested or supported.

■ All DIMMs within the B250 M2 server should use the same clock frequencies. Mixing clock

frequencies is not supported.

■ If the system has two CPUs, the DIMM slots for both CPUs should be populated in an identical

manner.

■ Populate DIMMs of different size and organization in separate memory channels. Populating

different sized DIMMs within a channel is not supported. For example you cannot put

single-rank 4GB DIMMs in the same channel as dual-rank 4GB DIMMs.

■ The B250 M2 server needs at least one DIMM pair installed for CPU 1 or CPU 2.

■ Carefully match CPU and DIMM speed. If the CPU and DIMM speeds do not match, the system

runs at the slower of the two speeds.

■ B250 M2 server memory is always sold as a correctly matched pair with identical

manufacturer, type, speed, and size, intended to be installed together in the two paired

banks of a single UCS Server memory channel. Mixing of unpaired DIMMs (even with other

DIMMs sold under the same product ID) will result in a memory errors should a mismatch

occur. When installing DIMMs in a B250 M2, you must add matched pairs to the channel slots

Number of

DIMMs

DIMM Placement in Numbered/Colored DIMM Slots

(Channel F not used with memory mirroring)

CPU1

4 (A0, A1) mirrored to (B0, B1)

8 (A0, A1, A2, A3) mirrored to (B0, B1, B2, B3)

16 (A0, A1, A2, A3, A4, A5, A6, A7) mirrored to (B0, B1, B2, B3, B4, B5, B6, B7)

CPU2

4 (D0, D1) mirrored to (E0, E1)

8 (D0, D1, D2, D3) mirrored to (E0, E1, E2, E3)

16 (D0, D1, D2, D3, D4, D5, D6, D7) mirrored to (E0, E1, E2, E3, E4, E5, E6, E7)

NOTE: System performance is optimized when the DIMM memory type and the DIMM

quantity is equal for both CPUs.