Specifications

4
OL-4923-01 B0
• Providing Simple Network Management Protocol (SNMP) management and the interface between
the console and Telnet
The high-speed switching section of the RSP2 communicates with and controls the interface processors
on the high-speed CyBus. This switching section decides the destination of a packet and switches it
based on that decision. The RSP2 uses a 16-million-instructions-per-second (mips) processor to provide
high-speed, autonomous switching and routing.
The RSP2 installs in the following slots on your Cisco 7000 or Cisco 7500 series router:
• Slot 4 in the Cisco 7505 router
• Slots 2 and 3 in the Cisco 7507 router
• Slots 6 and 7 in the Cisco 7513 router
Figure 1 RSP2 (Front-Panel View)
Note A bank of hardware (Media Access Control [MAC]-layer) addresses for the interface ports is contained
in an NVRAM device on the router backplane.
Figure 2 Route Switch Processor (RSP2)
CPU
The CPU used in the RSP2 is a Mips R4600 Reduced Instruction Set Computing (RISC) processor with
an external clock speed of 50 MHz, and an internal clock speed of 100 MHz.
H7189
ROUTE SWITCH PROCESSOR 4
SLAVE/MASTER
CPU HALT
RESET
ACTIVE
STANDBY
SLOT 1
SLOT 0
NORMAL
AUX
CONSOLE
H3105
CPU
Flash memory
SIMM holder
Console port
Auxiliary port
NVRAM
ROM monitor
(boot ROM)
U1
U12
U4
U30
U18
Bus connector
Bank 0
Bank 1
PC Card slots
slot 0: bottom
slot 1: top
SIMM
s
M
D
A
M
U33
U21