Specifications

HSSI Configuration Examples

Configuring Serial Interfaces IC-117

Conﬁgure Speciﬁc IP Addresses for an Interface Example

This example shows how to conﬁgure the access server so that it will use the default address pool on

all interfaces except interface 7, on which it will use an address pool called lass:

ip address-pool local

ip local-pool lass 172.30.0.1

async interface

interface 7

peer default ip address lass

HSSI Conﬁguration Examples

The following example show a simple conﬁguration for a HSSI port adapter on a Cisco 7500 series

router:

Router# configure terminal

Router(config)# interface hssi 2/0/0

Router(config-if)# ip address 1.1.1.10 255.255.255.0

Router(config-if)# description To San Jose, circuit ID 1234

Router(config-if)# no ip mroute-cache

Router(config-if)# exit

Router(config)# exit

Router#

The following example shows how to conﬁgure a 1-port HSSI network module on a Cisco 3600

series router. Both sides of the network connection need to be conﬁgured:

interface hssi 0/0

ip address 10.1.1.1 255.255.255.0

hssi internal-clock

no fair-queue

no shutdown

interface hssi 1/0

ip address 10.1.1.2 255.255.255.0

hssi internal-clock

no fair-queue

no shutdown

In this example:

• The interface hssi command speciﬁes a HSSI interface and changes the conﬁguration mode from

global to interface.

• The ip address command assigns an IP address to this interface.

• The hssi internal-clock command sets the HSSI clock source.

• The no fair-queue command disables fair queueing, which is enabled by default. This optimizes

HSSI performance.

• The no shutdown command enables the port.

Channelized T3 Interface Processor Conﬁguration Examples

The examples in this section show how to conﬁgure the Channelized T3 Interface Processor

(CT3IP). The ﬁrst example shows how to conﬁgure two of the T1 channels of the channelized T3

controller. The second example shows how to conﬁgure one of the T1 channels of the channelized

T3 controller as an external port for further channelization on the Multichannel Interface Processor

(MIP).