Specifications
1-20
Cisco MGX 8800/8900 Series Software Configuration Guide
Release 5.1, Part Number OL-6482-01, Rev. A0, January 25, 2005
Chapter 1 Preparing for Configuration
Guidelines for Creating a Network Clock Source Plan
Figure 1-7 shows an example network clock source topology that uses master clock sources on different
switches.
Figure 1-7 Example Network Clock Source Topology with Two Master Clock Sources
In Figure 1-7, Switches 1 and 2 have BITS devices. Switch 1 operates as the master and distributes its
BITS clock source over NNI trunks to Switches 2 through 4. Switch 2 is the standby master and receives
its primary clock signal over the NNI trunk from Switch 1. As long as Switch 1 and its primary BITS
clock source are operating correctly, the entire network is synchronized to the BITS clock source from
Switch 1.
The secondary clock source for the network is the Switch 2 BITS clock source, and all other switches
are configured to use the NNI trunks from Switch 2 as their secondary clock source. If Switch 1 or its
BITS clock source fails, all the switches start using the clock signals from Switch 2 for network
communications. This configuration preserves network sychronization when either a clock source or a
switch fails.
When a clock source fails and recovers, there are a couple of ways that the switch can revert back to the
recovered clock source. If the revertive option is enabled, the switch can automatically revert back to a
recovered primary source from the secondary source. If failures cause the tertiary clock source (the
internal Stratum-3 clock) to take over, the switch will revert to either a recovered primary or recovered
secondary clock source.
Note Regardless of the setting of the revertive option, the switch does revert back to a recovered primary clock
source if the secondary clock source fails. If the secondary clock source is functioning correctly and the
switch configuration does not support an automatic return to a recovered primary clock source, you can
manually switch back to the primary clock source by reconfiguring that clock source.
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Switch 3 Switch 4
Switch 1 –
Active master
clock source
Switch 2 –
Standby master
clock source
BITS
clock
source
BITS
clock
source
P = Primary clock source
S = Secondary clock source
P
P
S
SP
SP
S