Specifications

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Cisco MGX 8850 (PXM45) and MGX 8950 Software Configuration Guide
Release 3, Part Number 78-14788-01 Rev. C0, January 2004
Chapter 2 Configuring General Switch Features
Configuring the MPLS Controller
8850_LA.7.PXM.a > dsppnni-node
node index: 1 node name: 8850_LA
Level............... 56 Lowest.............. true
Restricted transit.. off Complex node........ off
Branching restricted on
Admin status........ up Operational status.. up
Non-transit for PGL election.. off
Node id...............56:160:47.00918100000000001a531c2a.00001a531c2a.01
ATM address...........47.00918100000000001a531c2a.00001a531c2a.01
Peer group id.........56:47.00.9181.0000.0100.0000.0000.00
8850_LA.7.PXM.a > dspspvcprfx
SPVC Node Prefix: 47.00918100000100001a531c2a
In the example above, the node ATM address does not conform to the peer group ID or the SPVC prefix,
so it must be advertised in addition to the SPVC prefix.
Configuring the MPLS Controller
The MPLS controller manages MPLS communications through the switch. Typically, the MPLS
controller is used with a PNNI controller. Both MPLS and PNNI controllers can be used on the same line.
Note Before entering the following command, you must log in as a user with SUPER_GP privileges or higher.
To enable and configure the MPLS controller, enter the following command:
mgx8850a.7.PXM.a > addcontroller <cntrlrId> i <cntrlrType> <lslot> [cntrlrName]
Table 2-6 describes the parameters for the addcontroller command.
Tip Remember to include the i option, which identifies the controller as an internal controller.
To display the MPLS controller configuration, enter the dspcontrollers command:
mgx8850a.7.PXM.a > dspcontrollers
Configuring Clock Sources
The “Network Clock Source Plan” section in Chapter 1, “Preparing for Configuration,” introduces
Building Integrated Timing System (BITS) clock sources and provides guidelines for developing a
network clock source plan. When the network clock source plan requires BITS clock sources on the
switch, you can use the procedure in this section to configure the BITS clock connections.
Figure 2-2 shows how BITS clock sources connect to the PXM45-UI-S3 back card.
The PXM45-UI-S3 clock source ports can be used to receive clock signals from either T1 or E1 lines;
the card does not support both line types simultaneously. These clock ports support stratum levels 1 to 3.