Specifications

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Cisco MGX 8850 (PXM45) and MGX 8950 Software Configuration Guide

Release 3, Part Number 78-14788-01 Rev. C0, January 2004

Chapter 1 Preparing for Configuration

Collecting Information

Figure 1-6 shows an example network clock source topology that uses two master clock sources.

Figure 1-6 Example Network Clock Source Topology with Two Master Clock Sources

In Figure 1-6, Switches 1 and 2 both use BITS clock sources. Switch 1 operates as the master and

distributes its BITS clock source over AXSM lines to Switches 2 through 4. Switch 2 is the standby

master and receives its primary clock signal over the AXSM line from Switch 1. As long Switch 1 and

its primary BITS clock source are operating correctly, the entire network is synchronized to the BITS

clock source from Switch 1.

In this example, the secondary clock source for Switch 2 is its BITS clock source, and all other switches

are configured to use the AXSM lines from Switch 2 as their secondary clock source. If Switch 1 or its

BITS clock source fails, all the switches, including Switch 1, start using the clock signals from Switch

2 for network communications. This configuration preserves network sychronization when either a clock

source or a switch fails.

To develop a network clock source plan, create a topology drawing and identify which switches serve as

active and standby master clock sources. For each switch that receives clock sources from other switches,

indicate which lines carry the primary and secondary clock signals.

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Switch 3 Switch 4

Switch 1 –

Active master

clock source

Switch 2 –

Standby master

clock source

BITS

clock

source

BITS

clock

source

P = Primary clock source

S = Secondary clock source