Specifications

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Cisco MGX 8850 (PXM45) and MGX 8950 Software Configuration Guide

Release 3, Part Number 78-14788-01 Rev. C0, January 2004

Chapter 1 Preparing for Configuration

Collecting Information

Figure 1-5 Example Network Clock Source Topology with a Single Master Clock Source

In Figure 1-5, Switch 1 provides the master network clock source to the rest of the network and uses

highly accurate external Building Integrated Timing System (BITS) clock sources to time its

transmissions. These BITS clock sources are T1 or E1 lines with Stratum-1, 2, or 3 clock signals.

Switch 1 uses one BITS line as the primary clock source and uses the secondary BITS source only if a

failure occurs on the primary BITS line. If the primary BITS line fails and recovers, the switch reverts

to the primary clock source if the revertive option was set when the primary clock was configured. If the

revertive option was not set, you must manually re-configure the primary clock.

Switches 2 through 5 synchronize their transmissions to Switch 1 with the master clock signal, which

they receive over AXSM lines. Switch 6 synchronizes its communications using the master clock source,

which is forwarded from Switch 3. In this topology, all switches synchronize to the same clock source,

and this configuration reduces the possibility that two switches might not be able to synchronize

communications.

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Switch 2 Switch 3

Switch 4 Switch 5

Switch 1 –

master clock

source

AXSM

lines with

clocks

AXSM

lines with

clocks

P = Primary clock source

S = Secondary clock source

Switch 6

BITS

clock

sources