Installation guide

Configuring Cisco G.SHDSL HWICs in Cisco Access Routers
Troubleshooting Cisco G.SHDSL HWICs
16
GEN 6 0 8 0 0
DBG 0 0 0 0 0
DSL 34 0 536537 0 0
IMA 0 0 0 0 0
EOC 0 0 0 0 0
******* HWIC Common Registers at B8000000 *******
HWIC ID: 0x1
HWIC Revision: 0x4
HWIC Status: 0x0
HWIC DDR TXCRC:0x0
HWIC Control: 0x8040
DDR Enable 1 Software Reset 0
Interrupt Module Reset 0 GDF Module Reset 0
DMA Module Reset 0 Flow Control Reset 0
IRQ2 Global Int Mask 0 IRQ1 Global Int Mask 1
DDR TXCRC Int Mask 0 DDR TXClk Loss Int Mask 0
TX Fifo Overrun Int Mask 0
HWIC Interrupt Event: 0x0
DDR TXCRC Int 0 DDR TXClk Loss Int 0
TX Fifo Overrun Int 0
HWIC Diag 1: 0x0
HWIC Diag 2: 0x1E0F
******* HWIC Host Registers at B8A00000 *******
Status (0x00):
Card Present Low 0 Graceful Stop Tx Complete 0
Config (0x00000806):
Hwic Reset 0 Hwic Host Reset 0
Hwic IRQ2 Type Err Hwic IRQ1 Type Net
Rx Queue Watermark Enable 0 Auto XOFF When Full 0
Rx Int On Last 0 Graceful Stop Tx 0
Generic Rx Enable 0 Generic Tx Enable 1
DDR Enable 1 Loopback 0
Error Interrupt Enable (0x37EFF):
Rx Done Error Int 1 Card Present Change Int 1
Hwic Int Frame Error Int 0x07 Tx First Last Error Int 1
Tx Done Error Int 1 IRQ2 Int 1
IRQ1 Int 0 Host Specific Error Int 1
Rx Overrun Int 1 DDR RxClk Missing Int 1
Reg RW Timeout Int 1 Reg RW Error Int 1
Rx CRC Int 1 Rx Format Error Int 1
DMA Error Int 1
Management Interrupt Enable (0xA000):
Hwic Int Frame Mgmt Int 0x0A
IRQ2 Int 0
IRQ1 Int 0 Graceful Stop Tx Int 0
Network Interrupt Enable (0x003F):
Rx Frame Drop Int 0 Generic Frame Tx Int 0
Generic Frame Rx Int 0 DMA Write Int 0
IRQ2 Int 0 IRQ1 Int 0
Int Frame Network Int 0x3F
Error Interrupt Event (0x0000):
Rx Done Error Event 0 Card Present Change Event 0
Hwic Int Frame Error Event 0x00 Tx First Last Error Event 0
Tx Done Error Event 0 IRQ2 Event 0
IRQ1 Event 0 Host Specific Error Event 0
Rx Overrun Event 0 DDR RxClk Missing Event 0
Reg RW Timeout Event 0 Reg RW Error Event 0
Rx CRC Event 0 Rx Format Error Event 0
DMA Error Event 0
Management Interrupt Event (0x0000):
Hwic Int Frame Mgmt Event 0x00
IRQ2 Int 0
IRQ1 Int 0 Graceful Stop Tx Event 0