Specifications

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Intel

Server Board

SE7501WV2

Technical Product Specification

Intel reference number C25653-001

Revision 1.0

December 2002

Enterprise Platforms and Services Division

Summary of content (169 pages)

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® Intel Server Board SE7501WV2 Technical Product Specification Intel reference number C25653-001 Revision 1.
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Revision History Intel® Server Board SE7501WV2 TPS Revision History Date 11/02 Revision Number 0.5 Modifications First draft for internal review based on the SE7500WV2 TPS 12/02 1.0 Production Release Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Intel® Server Board SE7501WV2 TPS Table of Contents Table of Contents 1. Introduction ..........................................................................................................17 2. SE7501WV2 Server Board Overview ..................................................................18 2.1 SE7501WV2 Feature Set........................................................................... 18 3. Functional Architecture ..............................................................................
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Table of Contents Intel® Server Board SE7501WV2 TPS 4.4 Hardware Initialization................................................................................ 41 4.5 Clock Generation and Distribution ............................................................. 41 4.6 PCI I/O Subsystem .................................................................................... 44 4.6.1 PCI Subsystem .......................................................................................... 44 4.6.
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Intel® Server Board SE7501WV2 TPS Table of Contents 5.3 Intelligent Platform Management Buses (IPMB) ........................................ 63 5.4 Inter Chassis Management Bus (ICMB)..................................................... 63 5.5 Error Reporting .......................................................................................... 64 5.5.1 Error Sources and Types ........................................................................... 64 5.5.2 PCI Bus Errors ................
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Table of Contents Intel® Server Board SE7501WV2 TPS 6.8 Automatic Detection of Video Adapters ..................................................... 76 6.9 Keyboard / Mouse Configuration................................................................ 77 6.9.1 Boot without Keyboard and/or Mouse ........................................................ 77 6.10 Floppy Drives ............................................................................................. 77 6.
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Intel® Server Board SE7501WV2 TPS Table of Contents 6.18.1 CMOS Reset.............................................................................................. 91 6.19 BIOS Updates ............................................................................................ 92 6.19.1 Flash Update Utility .................................................................................... 92 6.19.2 Loading the System BIOS.......................................................................... 93 6.
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Table of Contents Intel® Server Board SE7501WV2 TPS 6.34 Processor Bus Error................................................................................. 113 6.35 Single-Bit ECC Error Throttling Prevention .............................................. 113 6.36 System Limit Error ................................................................................... 114 6.37 Boot Event ............................................................................................... 114 6.
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Intel® Server Board SE7501WV2 TPS Table of Contents 6.44.4 Extended NVRAM Services ..................................................................... 129 6.44.5 IPMB Services ......................................................................................... 130 6.44.6 INT15h, Function DA20h, Subfunction 99h/9Ah/9Bh – Read/Write/Bus Master Write IMB .................................................................................................. 130 6.45 Multiple Processor Support (MPS)........
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Table of Contents Intel® Server Board SE7501WV2 TPS 8.5 PCI I/O Riser Slot Connector ................................................................... 143 8.6 Front Panel Connectors ........................................................................... 146 8.6.1 High Density 100-Pin Floppy / Front Panel / IDE Connector (J2G1)........ 148 8.6.2 VGA Connector........................................................................................ 150 8.6.3 SCSI Connectors ....................
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Intel® Server Board SE7501WV2 TPS Table of Contents 11.1.1 Product Safety Compliance...................................................................... 164 11.1.2 Product EMC Compliance........................................................................ 164 11.1.3 Product Regulatory Compliance Markings ............................................... 164 11.2 Electromagnetic Compatibility Notices ..................................................... 165 11.2.
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List of Figures Intel® Server Board SE7501WV2 TPS List of Figures Figure 1. Intel® Server Board SE7501WV2 Block Diagram........................................... 20 Figure 2. Memory Sub-system Block Diagram ............................................................. 24 Figure 3. Memory Bank Label Definition ...................................................................... 26 Figure 4. Serial Port Mux Logic .....................................................................................
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Intel® Server Board SE7501WV2 TPS List of Tables List of Tables Table 1. Intel® Server Board SE7501WV2 Processor Support Matrix for 533MHz ....... 21 Table 2. Intel® Server Board SE7501WV2 Processor Support Matrix for 400MHz ....... 22 Table 3. Memory Bank Labels....................................................................................... 25 Table 4. P64-B Speeds ................................................................................................. 29 Table 5. P64-C Speeds ...........
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List of Tables Intel® Server Board SE7501WV2 TPS Table 31. Setup Utility Screen....................................................................................... 97 Table 32. Keyboard Command Bar ............................................................................... 97 Table 33. Main Menu Selections ................................................................................... 99 Table 34. Primary Master and Slave Adapters Sub-menu Selections ......................... 100 Table 35.
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Intel® Server Board SE7501WV2 TPS List of Tables Table 64. Three-beep Boot Block Memory Failure Error Codes.................................. 126 Table 65. Interrupt 15h Extensions.............................................................................. 127 Table 66. User Binary Area Scan Point Definitions ..................................................... 134 Table 67. User Binary Information Structure ............................................................... 135 Table 68.
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List of Tables Intel® Server Board SE7501WV2 TPS Table 97. Intel® Server Board SE7501WV2 Static Power Supply Voltage Specification160 Table 98. Intel® Server Board SE7501WV2 Dynamic Power Supply Voltage Specification.......................................................................................................... 160 Table 99. Voltage Timing Parameters ......................................................................... 161 Table 100. Turn On / Off Timing......................................
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Intel® Server Board SE7501WV2 TPS 1. Introduction Introduction The Intel® SE7501WV2 server board Technical Product Specification (TPS) provides a highlevel technical description for the Intel® SE7501WV2 server board. It details the architecture and feature set for all functional sub-systems that make up the server board.
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SE7501WV2 Server Board Overview 2. Intel® Server Board SE7501WV2 SE7501WV2 Server Board Overview The SE7501WV2 server board is a monolithic printed circuit board with features that were designed to support the high-density 1U and 2U server market. 2.1 SE7501WV2 Feature Set Two different SE7501WV2 server boards will be made available. One will provide an embedded Ultra-320* SCSI interface and the other will provide an embedded ATA-100* “Value-Raid” interface.
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Intel® Server Board SE7501WV2 TPS • • • • • • • SE7501WV2 Server Board Overview - Flash ROM device for system BIOS: Intel® 32-megabit 28F320C3 Flash ROM Two external Universal Serial Bus (USB) ports with an additional internal header providing two optional USB ports for front panel support One external low-profile RJ45 serial port. An internal header is also available providing an optional serial port.
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SE7501WV2 Server Board Overview Intel® Server Board SE7501WV2 Figure 1. Intel® Server Board SE7501WV2 Block Diagram Revision 1.
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Intel® Server Board SE7501WV2 TPS 3. Functional Architecture Functional Architecture This chapter provides a high-level description of the functionality distributed between the architectural blocks of the SE7501WV2 server board. 3.1 Processor and Memory Subsystem The E7501 chipset provides a 36-bit address, 64-bit data processor host bus interface, operating at 400MHz and 533Mz in the AGTL+ signaling environment.
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Functional Architecture Intel® Server Board SE7501WV2 Table 2. Intel® Server Board SE7501WV2 Processor Support Matrix for 400MHz Speed (MHz) 400MHz 2.8 GHz 2.8 GHz 2.8GHz (1U) 2.6 GHz 2.6 GHz 2.6 GHz (1U) 2.4 GHz 2.4 GHz 2.4 GHz 2.4 GHz (1U) 2.2 GHz 2.2 GHz 2.2 GHz 2.2 GHz (1U) 2.0 GHz 2.0 GHz 1.8 GHz 1.8 GHz 1.
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Intel® Server Board SE7501WV2 TPS 3.1.1.2 Functional Architecture Reset Configuration Logic The BIOS determines the processor stepping, cache size, etc through the CPUID instruction. The requirements are that all processors in the system must operate at the same frequency, have the same cache sizes, and have the same VID. No mixing of product families is supported. On the SE7501WV2 platform, the BIOS is responsible for configuring the processor speeds.
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Functional Architecture Intel® Server Board SE7501WV2 Figure 2. Memory Sub-system Block Diagram 3.1.2.1 Memory DIMM Support The SE7501WV2 server board supports DDR266 compliant registered ECC DIMMs operating at 266MHz. (DDR200 DIMMs are supported when 400MHz processors are used.) Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported on the SE7501WV2 server board. A list of tested DIMMs will be made available.
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Intel® Server Board SE7501WV2 TPS Functional Architecture populated in order for the system to boot. If additional banks have less than two DIMMs, the memory for that bank(s) will not be available to the system. There are three banks of DIMMs, labeled 1, 2, and 3. Bank 1 contains DIMM locations 1A and 1B, Bank 2 contains 2A and 2B, and Bank 3 contains 3A and 3B. DIMM socket identifiers are marked with silkscreen next to each DIMM socket on the baseboard.
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Functional Architecture Intel® Server Board SE7501WV2 J5F1 J5F2 J5F3 J6F1 J6F2 J6F3 1B 1A 2B 2A 3B 3A Bank 1 Bank 3 Bank 2 Figure 3. Memory Bank Label Definition 3.1.2.3 I2C*Bus An I2C* bus connects the six DIMM slots to the ICH3-S and the BMC. This bus is used by the system BIOS to retrieve DIMM information needed to program the MCH memory registers which are required to boot the system. 3.1.2.
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Intel® Server Board SE7501WV2 TPS Functional Architecture double-bit error is detected during POST, the BIOS sends a Set DIMM State command to the BMC indicating that the DIMM LED is lit. 3.1.2.
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Functional Architecture • • Intel® Server Board SE7501WV2 The ICH3-S provides a 32-bit/33-MHz PCI bus hereafter called P32-A. The P64H2 provides two independent 64-bit, 133-MHz PCI-X buses hereafter called P64-B, and P64-C. This independent bus structure allows all three PCI buses to operate concurrently. 3.2.1 MCH Memory Architecture The MCH supports a 144-bit wide Memory Sub-system that can support a maximum of 12 GB (using 2 GB DIMMs).
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Intel® Server Board SE7501WV2 TPS 3.2.3 Functional Architecture P64H2 The P64H2 is a 567-ball FCBGA device and provides an integrated I/O bridge that provides a high-performance data flow path between the HI 2.0 and the 64-bit I/O subsystem. This subsystem supports peer 64-bit PCI-X segments. Because it has two PCI interfaces, the P64H2 can provide large and efficient I/O configurations. The P64H2 functions as the bridge between the HI and the two 64-bit PCI-X I/O segments.
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Functional Architecture • Intel® Server Board SE7501WV2 TPS Support for Zero Channel RAID (ZCR) or M-ROMB that allows the on board SCSI controller to be “hidden” from system and used by the RAID processor on the add-in card. The BIOS is responsible for setting the bus speed of the P64-C. The bus speed will always be set up to run at the speed of the slowest card installed. Table 5.
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Intel® Server Board SE7501WV2 TPS • • • • Functional Architecture APIC and 8259 interrupt controller Power management System RTC General purpose I/O The following are the descriptions of how each supported feature is used on the SE7501WV2 server board. 3.2.4.1 PCI Bus P32-A I/O Subsystem The ICH3-S provides a legacy 32-bit PCI subsystem and acts as the central resource on this PCI interface.
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Functional Architecture 3.2.4.5 Intel® Server Board SE7501WV2 TPS APIC The ICH3-S integrates an APIC that is used to distribute 24 interrupts. 3.2.4.6 Power Management One of the embedded functions of the ICH3-S is a power management controller. The SE7501WV2 server board uses this to implement ACPI-compliant power management features. The SE7501WV2 supports sleep states S0, S1, S4, and S5. 3.
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Intel® Server Board SE7501WV2 TPS 3.3.
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Functional Architecture 3.3.2.1 Intel® Server Board SE7501WV2 TPS Serial Port A Serial A is an optional port, accessed through a 9-pin internal header (J9A2). A standard DH-10 to DB9 cable can be used to direct Serial A out the back of a given chassis. The Serial A interface follows the standard RS232 pin-out. The baseboard has a Serial Port A silkscreen label next to the connector as well as a location designator of J9A2. The Serial A connector is located next to the P64-C low-profile PCI card slot.
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Intel® Server Board SE7501WV2 TPS Functional Architecture Serial B SIO Bus Exchange Serial A BMC 2 to 1 Mux Level Shifter Level shifter Header Rear RJ45 Figure 4. Serial Port Mux Logic 3.3.2.3.1 Rear RJ45 Serial B Port The rear RJ45 Serial B port is a fully functional serial port that can support any standard serial device.
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Functional Architecture Intel® Server Board SE7501WV2 TPS PIN 1 Pin 1 – DCD to Pin #7 Figure 5. J5A2 Jumper Block for DCD Signal For serial concentrators that require a DSR signal (Default), the J5A2 jumper block must be configured as follows: The Serial Port jumper in position 3 and 4. Pin 1 on the jumper is denoted by an arrow directly next to the jumper block. PIN 1 Pin 1 - DSR to Pin#7 Figure 6.
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Intel® Server Board SE7501WV2 TPS Functional Architecture For example, Modem applications typically use a DCD signal. In this case the user would use a DCD-configured adapter and set the jumper block as shown in Figure 5. 3.3.2.4 Floppy Disk Controller The floppy disk controller (FDC) in the SIO is functionally compatible with floppy disk controllers in the DP8473 and N844077. All FDC functions are integrated into the SIO including analog data separator and 16-byte FIFO.
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Configuration and Initialization 4. Intel® Server Board SE7501WV2 TPS Configuration and Initialization This section describes the configuration and initialization of various baseboard sub-systems as implemented on the SE7501WV2 server board. 4.1.1 Main Memory All installed memory greater than 1 MB is mapped to local main memory, up to the top of physical memory, which is located at 12 GB. Memory between 1 MB to 15 MB is considered standard ISA extended memory.
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Intel® Server Board SE7501WV2 TPS 4.1.3 Configuration and Initialization System Management Mode Handling ® The Intel E7501 MCH supports System Management Mode (SMM) operation in standard (compatible) mode. System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry to SMM, or other conditions, which can be configured using Intel E7501 PCI registers. 4.
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Configuration and Initialization 31 30 Intel® Server Board SE7501WV2 TPS 24 23 Reserved 16 15 Bus Number 11 10 Device 8 7 Functio 1 0 Register 0 0 Enable bit (‘1’ = enabled, ‘0’ = disabled) Figure 7. CONFIG_ADDRES Register 4.3.1.1 Bus Number PCI configuration space protocol requires that all PCI buses in a system be assigned a bus number. Furthermore, bus numbers must be assigned in ascending order within hierarchical buses.
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Intel® Server Board SE7501WV2 TPS Device Description 4.4 Configuration and Initialization Bus Device ID (Hex) 0A RMC Connector 1 P64H2 P2P Bridge A 2 1F P64H2 P2P Bridge B 2 1D Dual Gigabit NIC 3 07 PCI Slot 1B 3 08 PCI Slot 2B 3 09 PCI Slot 3B 3 0A SCSI 4 07 PCI Slot 1C 4 08 PCI Slot 2C 4 09 PCI Slot 3C 4 0A Hardware Initialization An Intel® Xeon™ processor system based on Intel E7501 MCH is initialized in the following manner. 1.
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Configuration and Initialization Intel® Server Board SE7501WV2 TPS • • • 100 MHz differentials: For INT3/FCPGA sockets, the MCH, and the ITP port. 66 MHz at 3.3 V logic levels: For MCH, P64H2, ICH3, and IDE RAID Controller clock 33.3 MHz at 3.3 V logic levels: Reference clock for ICH3, BMC, Video, SIO, and the IDE RAID controllers • 48MHz: ICH3-S, and SIO • 14.318 MHz at 3.
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Intel® Server Board SE7501WV2 TPS Configuration and Initialization Figure 8. Intel® Server Board SE7501WV2 Clock Distribution Revision 1.
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Configuration and Initialization 4.6 Intel® Server Board SE7501WV2 TPS PCI I/O Subsystem 4.6.1 PCI Subsystem The primary I/O bus for the SE7501WV2 server board is the PCI subsystem, with three independent PCI bus segments. The PCI bus complies with the PCI Local Bus Specification, Rev 2.2. The P32-A bus segment is directed through the ICH South Bridge while the two 64-bit segments, P64-B and P64-C, are directed through the P64H2 I/O Bridge.
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Intel® Server Board SE7501WV2 TPS Configuration and Initialization host bridge PCI interface (ICH) arbitration lines REQx* and GNTx* are special cases in that they are internal to the host bridge. The following table defines the arbitration connections. Table 12. P32-Arbitration Connections Baseboard Signals 4.6.
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Configuration and Initialization 4.6.3.2 Intel® Server Board SE7501WV2 TPS 23 On-board U320 SCSI controller 24 First slot of the riser card 25 Second slot of the riser card (for a 3-slot riser card) 26 Third slot of the riser card (for a 3-slot riser card) P64-B Arbitration The P64-B supports five PCI masters (the on-board gigabit ethernet controller, three slots on the 3-slot PCI Riser, and the P64H2). All PCI masters must arbitrate for PCI access using resources supplied by the P64H2.
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Intel® Server Board SE7501WV2 TPS Configuration and Initialization The ZCR add-in cards leverage the on-board SCSI controller along with their own built-in intelligence to provide a complete RAID controller subsystem on-board. The riser card and baseboard use an implementation commonly referred to as RAID I/O Steering (RAIDIOS) specification version 0.92 to support this feature.
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Configuration and Initialization • • • • • Intel® Server Board SE7501WV2 TPS A scatter/gather mechanism that supports both DMA and PIO IDE drives Support for ATA proposal PIO Mode 0, 1, 2, 3, 4, DMA Mode 0, 1, 2, and Ultra DMA Mode 0, 1, 2, 3, 4, 5 An IDE drive transfer rate capable of up to 100 MB/sec per channel A host interface that complies with PCI Local Bus Specification, Revision 2.
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Intel® Server Board SE7501WV2 TPS Configuration and Initialization Table 17.
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Configuration and Initialization 4.9.3 Intel® Server Board SE7501WV2 TPS MD[31..0] I/O Memory Data Bus RAS# O Row Address Select WE# O Write Enable Front Panel Video Memory When the SE7501WV2 server board is integrated into either a SR2300 or SR1300 chassis, the SE7501WV2 supports video through the front panel or the rear I/O panel. This is accomplished by routing video to two connectors. The rear video is provided through the standard DB15 video connector located in the rear I/O panel.
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Intel® Server Board SE7501WV2 TPS 4.11.1 Configuration and Initialization Legacy Interrupt Routing For PC-compatible mode, the ICH3-S provides two 82C59-compatible interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is presented to the processors, to which only one processor will respond for servicing. 4.11.1.
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Configuration and Initialization Intel® Server Board SE7501WV2 TPS bus). The I/O APICs monitor each interrupt on each PCI device including PCI. When an interrupt occurs, a message corresponding to the interrupt is sent across the FSB processors. The following table shows how the interrupts from the embedded devices and the PCI-X slots are connected. Table 20.
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Intel® Server Board SE7501WV2 TPS Configuration and Initialization IRQ12 IRQ13 IRQ14 IRQ15 Notes: LP = Low Profile FL = Full Length Revision 1.
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Server Management 5. Intel® Server Board SE7501WV2 TPS Server Management Network Activity LEDs Power LED System Identify LED Drive Activity/Fault LED Fault Status LED Power Button Reset Button System Identify Button Chassis Intrusion Front Panel NMI Switch The SE7501WV2 server management features are implemented using the Sahalee server board management controller chip. The Sahalee BMC is an ASIC packaged in a 156-pin BGA that contains a 32-bit RISC processor core and associated peripherals.
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Intel® Server Board SE7501WV2 TPS 5.1 Server Management Sahalee Baseboard Management Controller (BMC) The Sahalee BMC contains a 32-bit RISC processor core and associated peripherals used to monitor the system for critical events. The Sahalee BMC, packaged in a 156-pin BGA, monitors all power supplies, including those generated by the external power supplies and those regulated locally on the server board.
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Server Management Pin # Intel® Server Board SE7501WV2 TPS Pin Name Signal K13 XINT4 NIC1_SMBALERT_L Type/ Config input Description L14 XINT5 ICH3_SMI_BUFF_L input L12 XINT6 BMC_PCU12_PROCHOT_L input Prochot signal.
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Intel® Server Board SE7501WV2 TPS Pin # Pin Name BMC_A<8> Type/ Config output ADDR9 BMC_A<9> output ADDR10 BMC_A<10> output ADDR11 BMC_A<11> output M2 ADDR8 M3 L2 L3 Signal Server Management L1 ADDR12 BMC_A<12> output K4 ADDR13 BMC_A<13> output K2 ADDR14 BMC_A<14> output K3 ADDR15 BMC_A<15> output K1 ADDR16 BMC_A<16> output J2 ADDR17 BMC_A<17> output J3 ADDR18 BMC_A<18> output J1 ADDR19 BMC_A<19> output H4 ADDR20 BMC_A<20> output H2 ADDR21 BMC_A<21> o
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Server Management Pin # Intel® Server Board SE7501WV2 TPS Pin Name Signal H12 RTS1* BMC_ICMB_TX_ENB _L Type/ Config TP output Description G14 RX1 BMC_ICMB_RX input ICMB serial receive data G13 TX1 BMC_ICMB_TX output ICMB serial send data BMC speaker tone enable signal (for beeps) ICMB transceiver enable signal, asserted by BMC A12 TIC1_OUT BMC_SPKR_L TP output B12 TIC2_IN0 FAN_TACH1 input A13 TIC2_IN1 FAN_TACH2 input B13 TIC2_IN2 FAN_TACH3 input B14 TIC2_IN3 FAN_TACH4
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Intel® Server Board SE7501WV2 TPS Pin # Pin Name Signal Server Management D6 AVDD SB5V Type/ Config pwr/gnd M1 VDD5V SB5V pwr/gnd E14 VDD5V SB5V pwr/gnd E4 IOVCC SB3V pwr/gnd N3 IOVCC SB3V pwr/gnd L10 IOVCC SB3V pwr/gnd G11 IOVCC SB3V pwr/gnd D10 IOVCC SB3V pwr/gnd H3 COREVCC SB3V pwr/gnd M8 COREVCC SB3V pwr/gnd G12 COREVCC SB3V pwr/gnd C7 COREVCC SB3V pwr/gnd B3 AVS GND pwr/gnd A2 AVSUB GND pwr/gnd J4 IOGND GND pwr/gnd L6 IOGND GND pwr/gnd
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Server Management Intel® Server Board SE7501WV2 TPS Table 22.
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Intel® Server Board SE7501WV2 TPS Pin # Pin Name 38 AIN3 Signal P2V5 Server Management Type/ Config input Description Baseboard P2V5 monitor 39 AIN2 P5V_STBY_SCALED input External attenuator=1k/(1k+1k)=0.5 40 AIN1 P1V8_STBY input Baseboard P1V8_STBY monitor 41 AIN0 P3V3_VAUX input External attenuator=499k/(499+365~=0.58 42 THERM*/GPIO16 TP_HEC5_GPIO16 gpio This pin does not yet have a specified connection.
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Server Management Intel® Server Board SE7501WV2 TPS Near the end of POST, before the option ROMs are initialized, the BIOS disables the FRB-2 timer in the BMC. If the system contains more than 1 GB of memory and the user chooses to test every DWORD of memory, the watchdog timer is disabled before the extended memory test starts, because the memory test can take more than 6 minutes under this configuration.
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Intel® Server Board SE7501WV2 TPS 5.2.3 Server Management Soft Reset A soft reset causes the processors to begin execution in a known state without flushing caches or internal buffers. Soft resets can be generated by the keyboard controller located in the SIO, by the ICH3-S, or by the operating system. 5.3 Intelligent Platform Management Buses (IPMB) Management controllers (and sensors) communicate on the I2C-based Intelligent Platform Management Bus.
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Server Management 5.5 Intel® Server Board SE7501WV2 TPS Error Reporting This section documents the types of system bus error conditions monitored by the SE7501WV2 board set. 5.5.1 Error Sources and Types One of the major requirements of server management is to correctly and consistently handle system errors.
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Intel® Server Board SE7501WV2 TPS 5.5.5.1 Server Management DIMM LEDs One LED for each DIMM will be illuminated if that DIMM has an uncorrectable or multi-bit memory ECC. These LEDs will maintain the same state across power switch power down or loss of AC. These LED’s will only be reset when a Front Panel Reset is performed with main power available to the system or under control of an IPMI command. 5.5.5.2 CPU LEDs There is one LED for each CPU.
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Server Management 5.5.5.5.1 Intel® Server Board SE7501WV2 TPS System Status Indications Critical Condition A critical condition is any critical or non-recoverable threshold crossing associated with the following events: • Temperature, Voltage, or Fan critical threshold crossing • Power Subsystem Failure. The BMC asserts this failure whenever it detects a power control fault (e.g.
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Intel® Server Board SE7501WV2 TPS 5.5.5.7 Server Management POST Code Diagnostic LEDs To help diagnose POST failures, a set of four bi-color diagnostic LEDs is located on the back edge of the baseboard. Each of the four LEDs can have one of four states: Off, Green, Red, or Amber. During the POST process, each light sequence represents a specific Port-80 POST code. If a system should hang during POST, the diagnostic LEDs will present the last test executed before the hang.
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Server Management Intel® Server Board SE7501WV2 TPS Diagnostic LED Decoder G=Green, R=Red, A=Amber Hi Description Low 26h Off G A Off Read Microcode updates from BIOS ROM. 28h G Off R Off Initializing the processors. Set up processor registers. Select least featured processor as the BSP. 2Ah G Off A Off Go to Big Real Mode 2Ch G G R Off Decompress INT13 module 2Eh G G A Off Keyboard Controller Test: The keyboard controller input buffer is free.
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Intel® Server Board SE7501WV2 TPS Diagnostic LED Decoder G=Green, R=Red, A=Amber Hi Server Management Description Low 68h G R R Off Activate ADM: The display mode is set. Displaying the power-on message next. 6Ah G R A Off Initialize language module. Display splash logo. 6Ch G A R Off Display Sign on message, BIOS ID and processor information.
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Server Management Intel® Server Board SE7501WV2 TPS Diagnostic LED Decoder G=Green, R=Red, A=Amber Hi Description Low A2h R Off A Off Set Base Expansion Memory Size A4h R G R Off Program chipset setup options, build ACPI Tables, build INT15h E820h table A6h R G A Off Set Display Mode A8h A Off R Off Build SMBIOS table and MP tables. AAh A Off A Off Clear video screen.
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Intel® Server Board SE7501WV2 TPS 6. BIOS BIOS This section describes the BIOS-embedded software for the SE7501WV2 server board. This section also describes BIOS support utilities that are required for system configuration (ROM resident) and flash ROM update (not ROM resident). The BIOS contains standard PCcompatible basic input/output (I/O) services and standard Intel® server features. The BIOS is implemented as firmware that resides in the flash ROM.
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BIOS Intel® Server Board SE7501WV2 TPS boot from devices in the order specified by Setup. BIOS Setup also allows the C: drive to be any hard drive that is controlled by a Boot BIOS Specification compliant option ROM BIOS, including drives attached to the on-board SCSI controller or on-board IDE. Hard drives that are controlled by non-BBS compliant devices may appear under a different name, based on the BIOS vendor.
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Intel® Server Board SE7501WV2 TPS BIOS • Intel® Xeon™ running at 533MHz Front Side Bus only supports DDR266 DIMMs. Running these processors with DDR200 DIMMs is an unsupported configuration. • When Front Side Bus (FSB) is running at 400MHz, DDR266 DIMMs will be run at 200MHz (see Section 3.2 of the BIOS EPS for FSB speed details). • When FSB is running at 533MHz, DDR200 DIMMs will result in a BIOS error beep code.
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BIOS 6.3.3 Intel® Server Board SE7501WV2 TPS ECC Initialization Because only ECC memory is supported, the BIOS must initialize all memory locations before using them. The BIOS uses the auto-initialize feature of the MCH to initialize ECC. 6.3.4 Memory Remapping During POST memory testing, the detection of single-bit and multi-bit errors in DIMM banks is enabled. If a single-bit error is detected, a single DIMM number will be identified.
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Intel® Server Board SE7501WV2 TPS • • • • BIOS Advanced Configuration and Power Interface Specification PCI Local Bus Specification PCI BIOS Specification System Management BIOS Reference Specification In addition, refer to the relevant sections of the following specifications: • • • Extended System Configuration Data Specification Plug and Play ISA Specification Plug and Play BIOS Specification 6.5.
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BIOS 6.5.3 Intel® Server Board SE7501WV2 TPS PCI Auto-Configuration The system BIOS supports the INT 1Ah, AH = B1h functions, in conformance with the PCI Local Bus Specification, Revision 2.1. The system BIOS also supports the 16- and 32-bit protected mode interfaces as required by the PCI BIOS Specification, Revision 2.1. Beginning at the lowest device, the BIOS uses a “depth-first” scan algorithm to enumerate the PCI buses.
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Intel® Server Board SE7501WV2 TPS 6.9 BIOS Keyboard / Mouse Configuration The BIOS will support either a mouse or a keyboard in the single PS/2 connector. The BIOS will support both a keyboard and mouse if a Y-cable is used with the single PS/2 connector. The devices are detected during POST and the keyboard controller is programmed accordingly. Hot plugging of a keyboard from the PS/2 connector using DOS is supported by the system. 6.9.
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BIOS Intel® Server Board SE7501WV2 TPS Note: The recovery BIOS requires a 1.44 MB media in a 1.44 MB floppy drive or LS-120 drive. 6.11 Universal Serial Bus (USB) The SE7501WV2 server BIOS supports USB keyboard, mouse and boot devices. The SE7501WV2 server platform contains two USB host controllers. Each host controller includes the root hub and two USB ports.
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Intel® Server Board SE7501WV2 TPS 6.12.2 BIOS Advanced Configuration and Power Interface (ACPI) The primary role of the ACPI BIOS is to supply the ACPI Tables. POST creates the ACPI Tables and locates them above 1 MB in extended memory. The location of these tables is conveyed to the ACPI-aware operating system through a series of tables located throughout memory. The format and location of these tables is documented in the publicly available ACPI specification.
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BIOS Intel® Server Board SE7501WV2 TPS The S5 state is equivalent to an operating system shutdown. No system context is saved. 6.12.3 Wake Events The system BIOS is capable of configuring the system to wake up from several sources under a non-ACPI configuration, such as when the operating system does not support ACPI. The wake up sources are described in Table 27. Under ACPI, the operating system programs the hardware to wake up on the desired event.
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Intel® Server Board SE7501WV2 TPS BIOS in the BMC starting the power-up sequence. Since the processors are not executing, the BIOS does not participate in this sequence. The hardware receives power good and reset from the BMC and then transitions to an ON state. 6.12.4.2 On to Off (Legacy) The ICH3 is configured to generate an SMI due to a power button event. The BIOS services this SMI and sets the state of the machine in the chipset to the OFF state.
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BIOS • • • Intel® Server Board SE7501WV2 TPS WFM 2.0 items per the server checklist supplied in the WfM specification. INT15h functions 2500h, 2501h and 2502h as required. Support for and display of F12 Network boot POST hot key. 6.12.6 PXE BIOS Support This section discusses host system BIOS support required for PXE compliance and how PXE boot devices (ROMs) and PXE Network Boot Programs (NBPs) use it. 6.12.6.
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Intel® Server Board SE7501WV2 TPS 6.13.1 BIOS Operation When redirecting the console through a modem as opposed to a null modem cable, the modem needs to be configured with the following: • Auto-answer (for example, ATS0=2, to answer after two rings) • Modem reaction to DTR set to return to command state (e.g., AT&D1).
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BIOS Intel® Server Board SE7501WV2 TPS emulation supported by the BIOS. There are two non-overlapping terminal emulation systems supported simultaneously by Intel BIOS. These are known as VT100+ and a PC-ANSI. Microsoft prescribes a terminal emulation that they call VT100+ for use with Microsoft* systems. Microsoft* Windows* systems will interpret input sequences and other character sequences using this terminal emulation interpretation.
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Intel® Server Board SE7501WV2 TPS Key BIOS F11 PC-ANSI OZ VT100+ ! Shift Ctrl NS NS Alt NS F12 O1 @ NS NS Print Screen NS NS NS NS NS Scroll Lock NS NS NS NS NS NS Pause NS NS NS NS NS Insert [L + NS NS NS Delete (7Fh) - NS NS NS Home [H h NS NS NS End [K k NS NS NS Pg Up [M ? NS NS NS Pg Down [2J / NS NS NS Up Arrow [A [A NS NS NS Down Arrow <
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BIOS Intel® Server Board SE7501WV2 TPS Table 29.
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Intel® Server Board SE7501WV2 TPS BIOS Keyboard redirection operates through the use of the BIOS INT 16h handler. Software bypassing this handler does not receive redirected keystrokes. 6.14 Emergency Management Port (EMP) The SE7501WV2 provides a communication serial port with the BMC. The BMC controls a multiplexor that determines if the external RJ45 Serial 2 connector is electrically connected to the BMC or to the standard serial port of the Super I/O.
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BIOS Intel® Server Board SE7501WV2 TPS The BIOS provides setup options to configure the Service Partition type (the default is 98h), and the option for enabling and disabling the Service Partition boot. A remote agent can direct the BMC firmware to set the Service Partition boot request and reboot the system. Upon rebooting, the system BIOS checks for a service partition boot request.
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Intel® Server Board SE7501WV2 TPS BIOS address range 000F0000h to 000FFFFFh. This entry point encapsulates an intermediate anchor string, which is used by some existing DMI browsers. The total number of structures can be obtained from the SMBIOS entry-point structure. The system information is presented to an application as a set of structures that are obtained by traversing the SMBIOS structure table referenced by the SMBIOS entry-point structure.
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BIOS Intel® Server Board SE7501WV2 TPS Structure Type Memory Device (Type 17) Supported Comments Yes One record for each memory device slot, six total. DIMM3A/BANK3 will be the 1st entry DIMM3B/BANK3 will be the 2nd entry rd DIMM2A/BANK2 will be the 3 entry th DIMM2B/BANK2 will be the 4 entry th DIMM1A/BANK1 will be the 5 entry th DIMM1B/BANK1 will be the 6 entry BIOS will log memory SEL events during runtime that will contain a DIMM number that can be used to reference these tables.
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Intel® Server Board SE7501WV2 TPS 6.17.1 BIOS Quiet Boot Version 3.0 of the Hardware Design Guide for Microsoft Windows 2000 requires that the BIOS provide minimal startup display during BIOS POST. The system start-up must only draw the user’s attention in case of errors or when there is a need for user interaction. By default, the system must be configured so the screen display does not display memory counts, device status, etc., but presents a "clean" BIOS start-up.
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BIOS 1. 2. 3. 4. 5. Intel® Server Board SE7501WV2 TPS Power off the system, but leave the AC power connected so the 5 V standby is available. Assure that the CMOS clear jumper is in the ‘not clear’ position. Hold down the reset button for at least 4 seconds. While reset button is still depressed, press the on / off button. Simultaneously release both the on / off button and reset buttons.
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Intel® Server Board SE7501WV2 TPS 6.19.2 BIOS Loading the System BIOS The new BIOS is contained in .BIx files. The number of .BIx files is determined by the size of the BIOS area in the flash part. The number of files is constrained by the fact that the image and the utilities fit onto a single, 1.44 MB DOS-bootable floppy. These files are named as follows: • • • xxxxxxxx.BIO xxxxxxxx.BI1 xxxxxxxx.BI2 The first eight letters of each filename can be any value, but the files cannot be renamed.
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BIOS 1. 2. 3. 4. Intel® Server Board SE7501WV2 TPS Turn off the system power. Move the BIOS recovery jumper to the recovery state. Insert a bootable BIOS recovery diskette containing the new BIOS image files. Turn on the system power. The recovery BIOS boots from the DOS-bootable recovery diskette and emits one beep when it passes control to DOS. DOS then executes a special AUTOEXEC.BAT that contains “iFLASH” on the first line.
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Intel® Server Board SE7501WV2 TPS BIOS another BIOS update is performed. If a flash failure occurs, the BMC will switch back to the BIOS on the other partition, thus affecting a “Roll Back” as mentioned above. Unlike IFLASH / On-line updates, a recovery method will continue to change the BIOS on the primary partition. 6.20 BIOS and System Setup Two utilities are used to configure the BIOS and system resources, the BIOS Setup utility and the System Setup Utility.
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BIOS 6.20.2 Intel® Server Board SE7501WV2 TPS Setup Utility Operation The ROM-resident BIOS Setup utility is only used to configure on-board devices. The System Setup Utility is required to configure added PCI cards. The BIOS Setup utility screen is divided into four functional areas. Table 31 describes each area. Revision 1.
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Intel® Server Board SE7501WV2 TPS BIOS Table 31. Setup Utility Screen Functional Area Keyboard Command Bar Description Located at the bottom of the screen or as part of the help screen. This bar displays the keyboard commands supported by the Setup utility. Menu Selection Bar Located at the top of the screen. Displays the various major menu selections available to the user. The server Setup utility major menus are: Main Menu, Advanced Menu, Security Menu, Server Menu, Boot Menu, and the Exit Menu.
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BIOS Intel® Server Board SE7501WV2 TPS Key ↑ Option Select Item Description The up arrow is used to select the previous value in a pick list, or the previous options in a menu item's option list. The selected item must then be activated by pressing the Enter key. ↓ Select Item The down arrow is used to select the next value in a menu item’s option list, or a value field’s pick list. The selected item must then be activated by pressing the Enter key.
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Intel® Server Board SE7501WV2 TPS BIOS These and associated sub-menus are described in the following sections. 6.20.2.4 Main Menu Selections The following tables describe the available functions on the top-level menus and on various sub-menus. Default values are highlighted. Table 33. Main Menu Selections Feature System Time Option HH:MM:SS Description Set the System Time. System Date MM/DD/YYYY Set the System Date. Floppy A Not Installed Selects Diskette Type. 1.44 / 1.2 MB 3½” 2.
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BIOS Intel® Server Board SE7501WV2 TPS Table 34. Primary Master and Slave Adapters Sub-menu Selections Feature Type LBA Mode Control Multi-Sector Transfer PIO Mode Ultra DMA Option None Auto Disabled Enabled Description Auto allows the system to attempt auto-detection of the drive type. None informs the system to ignore this drive. Disabled by default if no devices are detected, otherwise the setting is auto detected This field is informational only.
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Intel® Server Board SE7501WV2 TPS BIOS Table 36. Advanced Menu Selections Feature PCI Configuration Option N/A Selects sub-menu. Peripheral Configuration N/A Selects sub-menu. Memory Configuration N/A Selects sub-menu. Advanced Chipset Control N/A Selects sub-menu. May not be present, if there are no advanced chipset settings under user control. Boot-time Diagnostic screen Disabled Enabled If enabled, the boot diagnostic screen is displayed during POST.
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BIOS Intel® Server Board SE7501WV2 TPS Table 39. PCI Device, Embedded Devices Feature USB Function Option Disabled On-board NIC Disabled Enabled Enabled Description If disabled, the USB controllers are turned off and the device resources are hidden from the system. If disabled, embedded NICs are turned offand the device resourses are hidden from the system. On-board NIC 1 ROM Enabled Disabled If enabled, initialize NIC 1 expansion ROM.
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Intel® Server Board SE7501WV2 TPS Legacy USB support Disabled Keyboard only BIOS If disabled, legacy USB support is turned off at the end of the BIOS POST. Auto Keyboard and Mouse Front Panel USB Disabled If disabled, the front panel USB ports are inactive. Enabled Table 41. Memory Configuration Menu Selections Feature Extended Memory Test Option Description Selects the size of step to use during Extended RAM tests.
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BIOS Intel® Server Board SE7501WV2 TPS Feature Secure Mode Timer Option 1 minute 2 minutes 5 minutes 10 minutes 20 minutes 60 minutes 120 minutes Description Period of key/PS/2 mouse inactivity specified for Secure Mode to activate. A password is required for Secure Mode to function. Has no effect unless at least one password is enabled. Secure Mode Hot Key (Ctrl-Alt- ) [Z] [L] Key assigned to invoke the secure mode feature. Cannot be enabled unless at least one password is enabled.
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Intel® Server Board SE7501WV2 TPS Boot Monitoring BIOS Sets the amount of time the OS Watchdog timer is programmed with. If disabled, the OS Watchdog timer is not programmed. BIOS programs this value in the BMC when setting the OS Watchdog timer at the end of POST. This feature is not available if HD OS Boot timeout or PXE OS Boot timeout is enabled.
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BIOS Intel® Server Board SE7501WV2 TPS Table 45. Serial Console Redirection Sub-menu Selections Feature BIOS Redirection Port Option Disabled Serial 1 (DB-9) Description Selects the Serial port to use for BIOS Console Redirection. “Disabled” completely disables BIOS Console Redirection. Serial 2 (RJ45) ACPI Redirection Port Disabled Serial 1 (DB-9) Selects the Serial port to use for ACPI Headless Console Redirection. “Disabled” completely disables ACPI Headless Console Redirection.
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Intel® Server Board SE7501WV2 TPS BIOS Table 47. Fault Resilient Boot Sub-menu Selections Feature Late POST Timeout Option Disable 5 minutes 10 minutes 15 minutes 20 minutes Description Controls the timeout value for addin PCI cards to be detected and execute their option ROMs. Falut Resilient Booting Stay ON Reset Poweroff Controls the FRB policy upon timeout for Late POST timeout, Hard Disk OS Boot Timeout, and PXE OS Boot Timeout.
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BIOS Intel® Server Board SE7501WV2 TPS Boot Priority 2 Device Hard Drive Description Attempt to boot from a hard drive device. 4 ATAPI CDROM Drive Attempt to boot from an ATAPI CD-ROM drive. 5 (any) SCSI CD-ROM Drive Attempt to boot from a SCSI CD-ROM containing bootable media. This entry will appear if there is a bootable CD-ROM that is controlled by a BIOS Boot Specification compliant SCSI option ROM. 6 PXE UNDI Attempt to boot from a network.
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Intel® Server Board SE7501WV2 TPS BIOS 6.21 BIOS Security Features The SE7501WV2 server BIOS provides a number of security features. This section describes the security features and operating model. Note: The SE7501WV2 server board has the ability to boot from a device attached to the USB port, such as a floppy disk, disk drive or CD-ROM, or ZIP* drive, even if it is attached through a hub. The security model is not supported when booting to a USB device. 6.21.
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BIOS Mode Password on boot Fixed disk boot sector Intel® Server Board SE7501WV2 TPS Entry Method/ Event Power On/Reset Power On/Reset Entry Criteria User • Password set and password on boot • enabled and Secure Boot Disabled in setup Set feature to Write Protect in Setup Behavior System halts for user Password before scanning option ROMs. The system is not in secure mode. Exit Criteria User Password No mouse or keyboard input is accepted except the password.
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Intel® Server Board SE7501WV2 TPS BIOS 6.23 Inactivity Timer If the inactivity timer function is enabled, and no keyboard or mouse actions have occurred for the specified time-out period, the following occurs until the user password is entered: • • • • PS/2 keyboard and PS/2 mouse input is disabled. PS/2 keyboard lights start blinking.
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BIOS Intel® Server Board SE7501WV2 TPS 6.29 PS/2 Keyboard and Mouse Lock Keyboard and/or mouse devices attached to the PS/2 connector are unavailable while the system is in secure mode. The keyboard controller will not pass any keystrokes or mouse movements to the system until the correct user password is entered. Note: Because secure mode has direct control of the keyboard controller and is able to secure access to the system via the PS/2 connector, the USB ports are not under secure mode control.
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Intel® Server Board SE7501WV2 TPS BIOS Sensors are managed by the BMC. The BMC is capable of receiving event messages from individual sensors and logging system events. Refer to the SE7501WV2 BMC EPS for additional information concerning BMC functions. 6.32 SMI Handler The SMI handler is used to handle and log system level events that are not visible to the server management firmware. If the SMI handler control bit is disabled in Setup, SMI signals are not generated on system errors.
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BIOS Intel® Server Board SE7501WV2 TPS 6.36 System Limit Error The BMC monitors system operational limits. It manages the A/D converter, defining voltage and temperature limits as well as fan sensors and chassis intrusion. Any sensor values outside of specified limits are fully handled by BMC. The BIOS does not generate an SMI to the host processor for these types of system events.
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Intel® Server Board SE7501WV2 TPS BIOS If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC logs a watchdog expiration event showing an FRB2 timeout (if so configured). It then hard resets the system, assuming Reset was selected as the watchdog timeout action. The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan, prior to displaying a request for a Boot Password or prior to an Extensive Memory Test.
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BIOS Intel® Server Board SE7501WV2 TPS POST task that was executed before the FRB-2 timer expired. This information may be useful for failure analysis. The BMC maintains failure history for each processor in nonvolatile storage. Once a processor is marked “failed,” it remains “failed” until the user forces the system to retest the processor.
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Intel® Server Board SE7501WV2 TPS BIOS Figure 10. BIOS Boot Monitoring Flowchart Start Increment Counter Yes Option = "disabled"? No Yes No Option = "Always Reset"? Fail count >3? Yes No Option="Retry Yes Service Boot"? WD Expired w/ OS Load? No Yes No Clear counter Clear counter Yes No No Arm WD Timer in BMC Continue Boot Fail count >6? Valid SP? Valid SP? Yes Yes No Go Boot SP Revision 1.
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BIOS Intel® Server Board SE7501WV2 TPS 6.40 Logging Format Conventions The BIOS complies with Version 1.5 of the Intelligent Platform Management Interface Specification. IPMI specifications 0.9, 1.0, and 1.5 define the required use of all but two bytes in each event log entry, Event Data 2 and Event Data 3. An event generator can specify that these bytes contain OEM-specified values. The system BIOS uses these two bytes to record additional information about the error.
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Intel® Server Board SE7501WV2 TPS BIOS Table 54. Memory Error Event Data Field Contents Field Generator ID IPMI Definition 7:1 System software ID or IPMB slave address. 1=ID is system software ID 0=ID is IPMB slave address. BIOS-Specific Implementation If BIOS is the source: 7:4 0x3 for system BIOS 3:1 1 = Format revision, Revision of the data format for OEM data bytes 2 and 3, For this revision of the specification, set this field to 1. All other revisions are reserved for now.
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BIOS Intel® Server Board SE7501WV2 TPS 6.40.2 PCI Error Events The following table defines the data byte formats for PCI bus-related errors logged by the BIOS. Table 55. PCI Error Event Data Field Contents Field Generator ID 7:1 IPMI Definition System software ID or IPMB slave address. 1=ID is system software ID; 0=ID is IPMB slave address.
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Intel® Server Board SE7501WV2 TPS BIOS The following table provides examples of the event data fields for PCI device-related errors. Table 56. Examples of Event Data Field Contents for PCI Errors Error Type PCI PERR, failing device is not known Event Data 1 04 Event Data 2 0xFF Event Data 3 0xFF PCI SERR, failing device is not known 05 0xFF 0xFF PCI PERR, device 3, function 1 on PCI bus 5 reported the error 0xA4 0x05 0x19 An unknown device on PCI bus 0 reported the SERR 0x85 6.40.
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BIOS Field Event Data 3 Intel® Server Board SE7501WV2 TPS IPMI Definition 7:0 OEM code 3 or unspecified BIOS Specific Implementation For format rev 0, if this byte is specified, it contains bits 15:8 of the POST code at the time FRB-2 reset occurred (port 81 code). If the BIOS only uses one byte POST codes, this byte will always be zero. The following table provides examples of the event data fields for FRB-2 errors. Table 58.
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Intel® Server Board SE7501WV2 TPS BIOS Table 59.
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BIOS Intel® Server Board SE7501WV2 TPS Error Code 116 Hard disk 3 Error Error Message Pause on Boot Yes 117 CD-ROM disk 0 Error Yes 118 CD-ROM disk 1 Error Yes 119 CD-ROM disk 2 Error Yes 11A CD-ROM disk 3 error Yes 11B Date/Time not set Yes 11E Cache memory bad Yes 120 CMOS clear Yes 121 Password clear Yes 140 PCI Error Yes 141 PCI Memory Allocation Error Yes 142 PCI IO Allocation Error Yes 143 PCI IRQ Allocation Error Yes 144 Shadow of PCI ROM Failed Yes 145 P
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Intel® Server Board SE7501WV2 TPS Error Code BIOS Error Message Pause on Boot 8197 CPU Speed mismatch Yes 8198 Failed to load processor microcode Yes 8300 Baseboard Management Controller failed to function Yes 8301 Front Panel Controller failed to Function Yes 8305 Hotswap Controller failed to Function Yes 8420 Intelligent System Monitoring Chassis Opened Yes 84F1 Intelligent System Monitoring Forced Shutdown Yes 84F2 Server Management Interface Failed Yes 84F3 BMC in Update Mo
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BIOS Intel® Server Board SE7501WV2 TPS Recovery BIOS will generate two beeps and flash a POST code sequence of 0E9h, 0EAh, 0EBh, 0ECh, and 0EFh on the POST Progress Code LEDs. During recovery mode, video will not be initialized. One high-pitched beep announces the start of the recovery process. The entire process takes two to four minutes. A successful update ends with two high-pitched beeps. Failure is indicated by a long series of short beeps. 6.41.5 Bootblock Error Beep Codes Table 63.
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Intel® Server Board SE7501WV2 TPS Beep Code 3 07h-0Dh BIOS Diagnostic LED Decoder G=Green, R=Red, A=Amber Hi Low Off G G G G Off Off Off G Off Off G G Off G Off G Off G G G G Off Off G G Off G Meanings Generic memory error 3 0Eh G G G Off SMBUS protocol error 3 0Fh G G G G Generic memory error 6.
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BIOS Intel® Server Board SE7501WV2 TPS Call With Returns AH AL CL = DAh = 12h =0 =1 =2 =3 Disable cache Enable cache Read cache status Set Writeback Mode =0 =1 Cache Disabled Cache Enabled AH, bit 0 AH, bit 1 =0 =1 CX, bit 15 =0 =1 CX, bits 14:0 CF =0 =1 6.44.
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Intel® Server Board SE7501WV2 TPS 6.44.3 BIOS Processor Information Processor Information returns information about the system processors.
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BIOS Intel® Server Board SE7501WV2 TPS Returns 6.44.5 ES:DI = Pointer to data buffer CF = 0 Success = 1 Failure Error codes: AH = 1 Flash area not supported = 2 Flash write failed = 5 Invalid OEM index = 86h Function not supported = 88h Security failure IPMB Services The system BIOS provides real-mode calls to Read, Write, and Master Read/Write the IPMB. The Read and Write functions are used for all master/slave I2C devices on all buses.
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Intel® Server Board SE7501WV2 TPS • • • • • • • • BIOS MP table header Processor entries PCI bus entries I/O APIC entries Local interrupt entries System address space-mapping entries Bus hierarchy descriptor Compatibility bus address space modifier entries 6.45.2 Multiple Processor Support IA-32 processors have a microcode-based MP initialization protocol. On reset, all of the processors compete to become the bootstrap processor (BSP).
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BIOS Intel® Server Board SE7501WV2 TPS 6.46 Hyper-Threading Technology Refer to the Intel® NetburstTM Micro-architecture BIOS Writer’s Guide for details regarding the implementation of Hyper-Threading Technology-enabled processors. In addition to these requirements, the following are also implemented: • • • • Display of processors during POST. BIOS displays the number of physical processors detected. Display of processors during BIOS Setup. BIOS displays the corresponding physical processors.
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Intel® Server Board SE7501WV2 TPS BIOS • User binary code must be relocatable. It will be located within the first Megabyte. The user binary code should not make any assumptions about the value of the code segment. • User binary code will always be executed from RAM and never from flash. • The code in user binary should not hook critical interrupts, should not reprogram the chipset and should not take any action that affects the correct functioning of the system BIOS.
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BIOS Intel® Server Board SE7501WV2 TPS The following code fragment shows the header and format for a user binary: db 55h, 0AAh, 20h ; 8KB USER Area MyCode db CBh db 04h ; ; ; ; ; ; ; ; ; ; MUST be a FAR procedure Far return instruction Bit map to define call points, a 1 in any bit specifies that the BIOS is called at that scan point in POST First transfer address used to point to user binary extension structure Word Pointer to extension structure Reserved ; ; ; ; ; ; ; ; ; This is a list of 7 transf
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Intel® Server Board SE7501WV2 TPS 6.48.2 BIOS Format of the User Binary Information Structure Table 67. User Binary Information Structure Offset 0 Bit 0 Bit definition 1 if mandatory user binary, 0 if not mandatory. If a user binary is mandatory, it will always be executed. If a platform supports a disabling of the user binary scan through CU, this bit will override CU setting.
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SE7501WV2 ACPI Implementation Intel® Server Board SE7501WV2 TPS 7. SE7501WV2 ACPI Implementation 7.1 ACPI An ACPI aware operating system (OS) generates an SMI to request that the system be switched into ACPI mode. The BIOS responds by sending the appropriate command to the BMC to enable ACPI mode. The system automatically returns to legacy mode upon hard reset or power-on reset. The SE7501WV2 platform supports S0, S1, S4, and S5 states.
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Intel® Server Board SE7501WV2 TPS SE7501WV2 ACPI Implementation The power button input (FP_SLP_BTN*) will behave differently depending on whether or not the operating system supports ACPI. The sleep switch has no effect unless an operating system with ACPI support is running. If the operating system supports ACPI and the system is running, pressing the sleep switch causes an event. The operating system will cause the system to transition to the appropriate system state depending on the user settings.
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SE7501WV2 ACPI Implementation 7.1.2 Intel® Server Board SE7501WV2 TPS Wake up Sources (ACPI and Legacy) The SE7501WV2 server board is capable of wake up from several sources under a non-ACPI configuration, e.g., when the operating system does not support ACPI. The wake up sources are defined in the following table. Under ACPI, the operating system programs the ICH3-S and SIO to wake up on the desired event, but in legacy mode, the BIOS enables/disables wake up sources based on an option in BIOS Setup.
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Intel® Server Board SE7501WV2 TPS SE7501WV2 Connectors 8. SE7501WV2 Connectors 8.1 Power Connectors The power supply connection is obtained using a 24-pin connector, 5-pin connector and an 8pin connector. The following tables define the pin-outs of these connectors. Table 69. Power Connector Pin-out (J3J1) Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal +3.3Vdc +3.3Vdc GND +5Vdc GND +5Vdc GND PWR_OK 5VSB +12Vdc +12Vdc +3.3Vdc Pin 13 14 15 16 17 18 19 20 21 22 23 24 Signal +3.
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SE7501WV2 Connectors 8.2 Intel® Server Board SE7501WV2 TPS Memory Module Connector The SE7501WV2 server board has six DDR DIMM connectors and supports registered ECC DDR-200/266 modules. For additional DIMM information, refer to the DDR-200/266 Registered DIMM Specification. Table 72.
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Intel® Server Board SE7501WV2 TPS 8.3 SE7501WV2 Connectors Processor Socket The SE7501WV2 server board has two Socket 604 processor sockets. The following table provides the processor socket pin numbers and pin names. Table 73. Socket 604 Processor Socket Pinout Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
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SE7501WV2 Connectors Intel® Server Board SE7501WV2 TPS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
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Intel® Server Board SE7501WV2 TPS 8.4 SE7501WV2 Connectors System Management Headers 8.4.1 ICMB Header Table 74. ICMB Header Pin-out (J9B2) Pin 8.4.2 Signal Name Type Description 1 5 V standby Power +5 V Standby 2 Transmit Signal UART signals 3 Transmit Enable Signal UART signals 4 Receive Signal UART signals 5 Ground GND Ground OEM IPMB Header Table 75. IPMB Header Pin-out (J9C1) Pin 8.
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SE7501WV2 Connectors Pin 12 Intel® Server Board SE7501WV2 TPS Side B Ground Side A Ground Pin 60 Side B ACK64# Side A REQ64# 13 Ground Ground 61 +5 V +5 V 14 REQ2# 3.3 V AUX 62 +5 V +5 V 15 Ground RST# Connector Key Connector Key 16 CLK +5 V Connector Key Connector Key 17 Ground GNT# 63 Clock Slot2 Ground 18 REQ# Ground 64 Ground C/BE[7]# 19 +5 V PME# 65 C/BE[6]# C/BE[5]# 20 AD[31] AD[30] 66 C/BE[4]# +5 V 21 AD[29] +3.
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Intel® Server Board SE7501WV2 TPS Pin SE7501WV2 Connectors Side B Side A Pin Side B Side A Ground TMS 51 Connector Key Connector Key 4 IRQ4 TDI 52 AD[08] C/BE[0]# 5 +5 V +5 V 53 AD[07] +3.3 V 3 6 +5 V IRQ0 54 +3.
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SE7501WV2 Connectors Pin 48 8.6 Intel® Server Board SE7501WV2 TPS Side B AD[10] Side A Ground Pin 94 Side B Ground Side A Pull Down Front Panel Connectors A high density, 34-pin header (J1G4) and an SSI standard 24-pin header (J1H1) are provided to support a system front panel. The headers contain reset, NMI, power control buttons, and LED indicators. Table 78.
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SE7501WV2 Connectors Intel® Server Board SE7501WV2 TPS Table 79. SSI Compliant 24-pin Front Panel Connector Pinout (J1H1) Pin 8.6.
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Intel® Server Board SE7501WV2 TPS Pin Signal Name SE7501WV2 Connectors Pin Signal Name A19 FD_DSKCHG_L B19 GND A20 FD_WPD_L B20 FD_RDATA_L A21 FD_TRK0_L B21 GND A22 GND B22 FD_WDATA_L A23 FD_WGATE_L B23 GND A24 FD_DIR_L B24 FD_STEP_L A25 FD_DS0_L B25 GND A26 GND B26 FD_MTR0_L A27 FD_INDEX_L B27 GND A28 GND B28 V_Switch A29 FD_DENSEL0 B29 GND A30 GND B30 IDE_RESET_L A31 IDE_PDD<7> B31 GND A32 IDE_PDD<6> B32 IDE_PDD<8> A33 GND B33 IDE_PDD<9> A3
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SE7501WV2 Connectors 8.6.2 Intel® Server Board SE7501WV2 TPS VGA Connector The following table details the pin-out of the VGA connector (located on the rear I/O panel). Table 81. VGA Connector Pin-out (J8A1) Pin 8.6.
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Intel® Server Board SE7501WV2 TPS Connector Contact Number 8.6.
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SE7501WV2 Connectors Intel® Server Board SE7501WV2 TPS Pin 8.6.5 Signal Name Pin 28 Signal Name 11 NICB_MDI1P NICA_LINK_ACT 12 2.5V 29 NICA_SPEED_1 13 NICB_MDI0M 30 NICA_SPEED_2 14 2.5V 31 NICB_LINK_ACT_L 15 NICA_MDI0P 32 NICB_LINK_ACT 16 NICA_MDI1M 33 NICB_SPEED_1 17 2.5V 34 NICB_SPEED_2 ATA RAID Connectors The ATA-100 SE7501WV2 board provides two 40-pin low-density ATA-100 connectors. The pin-out for both connectors is identical and is listed in the following table.
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Intel® Server Board SE7501WV2 TPS SE7501WV2 Connectors Table 85. ATA-100 Legacy 40-pin Connector Pinout (J1G2) Pin 8.6.
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SE7501WV2 Connectors Intel® Server Board SE7501WV2 TPS Table 87. Optional USB Connection Header Pin-out (J1D3) Pin 1 2 3 4 5 6 7 8 9 10 8.6.
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Intel® Server Board SE7501WV2 TPS 8.6.8 SE7501WV2 Connectors Serial Port Connector Two serial ports are provided on the server board. • A low-profile RJ45 connector is located on the rear edge of the baseboard to supply Serial port B. The rear Serial port B is a fully functional serial port and will support any standard serial device as well as provide support for a serial concentrator. For those server applications that require a DB9 type serial connector, a 8-pin RJ45-to-DB9 adapter must be used.
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SE7501WV2 Connectors Intel® Server Board SE7501WV2 TPS Table 91. Keyboard and Mouse PS/2 Connector Pin-out (J6A1) Pin 1 2 3 4 5 6 8.7 8.7.1 Signal Name Keyboard Data Mouse Data GND Fused VCC Keyboard Clock Mouse Clock Miscellaneous Headers Fan Headers The SE7501WV2 server board provides two 3-pin fan headers. They are labeled “CPU1 Fan”, and “CPU2 Fan” and do not have variable speed fan power; they use direct 12 volts.
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Intel® Server Board SE7501WV2 TPS 9. Configuration Jumpers Configuration Jumpers This section describes configuration jumper options on the SE7501WV2 server board. 9.1 System Recovery and Update Jumpers The SE7501WV2 server board provides one 11-pin single inline header (J1D4), which provides a total of three 3-pin jumper blocks that are used to configure several system recovery and update options. CMOS CLEAR PASSWORD CLEAR RECOVERY BOOT Figure 11.
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Configuration Jumpers 9.2 Intel® Server Board SE7501WV2 TPS External RJ45 Serial Port Jumper Block The jumper block J5A2, located directly behind the external low profile RJ45 serial port, is used to configure either a DSR or a DCD signal to the connector. See Section 3.3.2.3 for additional information on serial port usage. Revision 1.
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Intel® Server Board SE7501WV2 TPS General Specifications 10. General Specifications 10.1 Absolute Maximum Ratings Operating an SE7501WV2 baseboard at conditions beyond those shown in the following table may cause permanent damage to the system. The table is provided for stress testing purposes only. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 95.
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General Specifications Intel® Server Board SE7501WV2 TPS SR1300 Chassis Device(s) 3.3V 5.V 12.V Processors -12.V 5.VSB 3.3VSB 13.A Memory DIMMs 5.9A Server Board 6.6A 2.6A .5A Fans .A 1.4A 1.8A Keyboard/Mouse .4A PCI Slots (standby on full height slots only) 2.1A 2.8A .5A Peripherals .5A .1A 2.6A 3.5A 8.4A 25.2A .1A Total Current 8.7A .5A 1.4A Total Power 28.7W 42.W 302.4W -6.W 7.W .2A Total Power .5W 367.7W 10.
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Intel® Server Board SE7501WV2 TPS General Specifications Vout V1 10% Vout V2 V3 Tvout Tvout_off rise Tvout_on Figure 12. Output Voltage Timing The following tables show the timing requirements for a single power supply being turned on and off via the AC input, with PSON held low and the PSON signal, with the AC input applied. The ACOK# signal is not being used to enable the turn on timing of the power supply. Table 99.
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General Specifications Intel® Server Board SE7501WV2 TPS Item Description Min Max Units T pson_pwok Delay from PSON# deactive to PWOK being de-asserted. Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on. 100 T pwok_off Delay from PWOK de-asserted to output voltages (3.3V, 5V, 12V, -12V) dropping out of regulation limits. 2 msec Tpwok_low Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal.
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Intel® Server Board SE7501WV2 TPS 10.3.2 General Specifications Voltage Recovery Timing Specifications The power supply must conform to the following specifications for voltage recovery timing under load changes: • Voltage shall remain within +/- 5% of the nominal set voltage on the +5 V, +12 V, 3.3 V, 5 V and -12 V output, during instantaneous changes in load.
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Regulatory and Integration Information Intel® Server Board SE7501WV2 TPS 11. Regulatory and Integration Information 11.1 Product Regulatory Compliance 11.1.1 Product Safety Compliance The SE7501WV2 server board complies with the following safety requirements: • • • • • • 11.1.
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Intel® Server Board SE7501WV2 TPS Regulatory and Integration Information 11.2 Electromagnetic Compatibility Notices 11.2.1 Europe (CE Declaration of Conformity) This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance. 11.2.
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Regulatory and Integration Information Intel® Server Board SE7501WV2 TPS ADVARSEL! Lithiumbatteri - Eksplosionsfare ved fejlagtig håndtering. Udskiftning må kun ske med batteri af samme fabrikat og type. Levér det brugte batteri tilbage til leverandøren. ADVARSEL Lithiumbatteri - Eksplosjonsfare. Ved utskifting benyttes kun batteri som anbefalt av apparatfabrikanten. Brukt batteri returneres apparatleverandøren. VARNING Explosionsfara vid felaktigt batteribyte.
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Intel® Server Board SE7501WV2 TPS Mechanical Specifications 12. Mechanical Specifications The following figure shows the SE7501WV2 server board mechanical drawing. MOLEX 3P RA FAN CONNECTOR FAN HEADER PROCESSOR POWER MOLEX 24P POWER CONN SIG PWR CONN ATX FRONT PANEL CONN FRONT PANEL CONN FLOPPY/FP/ATA CONN 6X DIMM SOCKETS IPMB CONN ATA66 IDE CONN 2X 5V 64BIT PCI CONN (3.
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Mechanical Specifications Intel® Server Board SE7501WV2 TPS 12.1 PCI Riser Cards The SE7501WV2 server board supports two peer 64-bit, PCI buses. Each provides a PCI riser slot that is capable of supporting either a 1-slot PCI riser card or a 3-slot PCI riser card. This will allow the 3.3V PCI and universal expansion cards to be physically parallel with the server board. 12.1.1 1-Slot 3.3V PCI Riser Card The 1-slot PCI riser card provides support for one 64-bit, 100 MHz, 3.3 V PCI card.
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Intel® Server Board SE7501WV2 TPS Appendix A: Glossary Appendix A: Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first with alpha entries following. Acronyms are then entered in their respective place, with non-acronyms following.
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Appendix A: Glossary Intel® Server Board SE7501WV2 Term Definition MT Mega transfers or million transactions Mux multiplexor NIC Network Interface Card NMI Non-maskable Interrupt OEM Original equipment manufacturer Ohm Unit of electrical resistance P32-A 32-bit PCI Segment P64-B Full Length 64/133 MHz PCI Segment P64-C low-profile 64/133 MHz PCI Segment P64H2 PCI 64bit Hub 2.