Specifications

Configure E1 R2 Voice Ports
Voice over IP for the Cisco AS5300 19
Verify E1 R2 Signalling Configuration
To verify the E1 R2 signalling configuration:
• Type the show controller e1 command to view the status for all controllers, or type the show
controller e1 number command to view the status for a particular controller. Make sure the status
indicates the controller is up (line 2 in the following example) and no alarms (line 4 in the
following example) or errors (lines 9 and 10 in the following example) have been reported.
5300# show controller e1 0
E1 0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
Version info of Slot 0: HW: 2, Firmware: 4, PLD Rev: 2
Manufacture Cookie is not programmed.
Framing is CRC4, Line Code is HDB3, Clock Source is Line Primary.
Data in current interval (785 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 13 15 minute intervals):
0 Line Code Violations, 0 Path Code Violations,
0 Slip Secs, 12 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 12 Unavail Secs
• To check the robbed-bit signalling status of each channel, type the debug serial interface
command and the show controller e1 command.
as5300#debug serial interface
Serial network interface debugging is on
as5300#show controller e1 0
E1 0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
Version info of Slot 0: HW:2, Firmware:4, PLD Rev:0
Manufacture Cookie Info:
EEPROM Type 0x0001, EEPROM Version 0x01, Board ID 0x43,
Board Hardware Version 1.0, Item Number 73-2218-4,
Board Revision A0, Serial Number 07805788,
PLD/ISP Version 0.0, Manufacture Date 19-Feb-1998.
Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line Primary.
Data in current interval (135 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail
Secs
Robbed bit signals state:
timeslots rxA rxB rxC rxD txA txB txC txD
1 0 0 0 1 0 1 0 1
2 0 0 0 1 0 1 0 1
3 0 0 0 1 0 1 0 1
4 1 0 0 1 1 0 0 1
5 1 0 0 1 1 0 0 1
6 0 0 0 1 0 1 0 1
7 1 0 0 1 1 0 0 1