Datasheet

5-18
Cisco ONS 15454 SDH Reference Manual, R7.0
October 2008
Chapter 5 Ethernet Cards
5.8 ML1000-2 Card
The ML1000-2 card provides two ports of IEEE-compliant, 1000-Mbps interfaces. Each interface
supports full-duplex operation for a maximum bandwidth of 2 Gbps per port and 4 Gbps per card. Each
port autoconfigures for full duplex and IEEE 802.3x flow control.
SFP modules are offered as separate orderable products for maximum customer flexibility. For details,
see the “5.11 Ethernet Card GBICs and SFPs” section on page 5-25.
Figure 5-7 shows the ML1000-2 card faceplate and block diagram.
Figure 5-7 ML1000-2 Faceplate and Block Diagram
ML-Series cards feature two SDH virtual ports with a maximum combined bandwidth of VC4-16c. Each
port carries an STM circuit with a size of VC3, VC4, VC4-2c, VC4-3c, VC4-4c, and VC4-8c. To configure
an ML-Series card SDH STM circuit, refer to the “Create Circuits and Low-Order Tunnels” chapter of
the Cisco ONS 15454 SDH Procedure Guide.
The ML-Series POS ports supports VCAT of SONET/SDH circuits and a software link capacity
adjustment scheme (SW-LCAS). The ML-Series card supports a maximum of two VCAT groups with
each group corresponding to one of the POS ports. Each VCAT group must be provisioned with two
circuit members. An ML-Series card supports VC-3-2v, VC-4-2v and VC-4-4c-2v. To configure an
ML-Series card SDH VCAT circuit, refer to the “Create Circuits and Low-Order Tunnels” chapter of the
Cisco ONS 15454 SDH Procedure Guide.
1
2
3
4
5
6
7
8
9
10
11
ACT
FAIL
ML100T
12
0
134622
BTC192
B
a
c
k
p
l
a
n
e
BPIA
Main
Rx
BPIA
Protect
Rx
BPIA
Main
Tx
BPIA
Protect
Tx
Processor
Daughter Card
(FLASHs,
SDRAMs)
Packet
Buffer
512Kx96
Packet
Buffer
512Kx96
SSRAM
2x512Kx36
ch0-1 ch4-5
Control Mem
512Kx32
Control Mem
512Kx32
Result Mem
512Kx32
DOS
FPGA
port
2
port
3
GMII
RGGI
RGGI
RGGI
RGGI
port
A
port
B
port
3
port
2
port
0
port
1
Serdes
Serdes
SFP
GBIC
Module
SFP
GBIC
Module
MAC 1 MAC 2
port
0
port
1
GMII
Panel Port 0
Panel Port 1