Datasheet

5-14
Cisco ONS 15454 SDH Reference Manual, R7.0
October 2008
Chapter 5 Ethernet Cards
5.6 ML100T-12 Card
determine whether to enable or disable flow control. For ML-Series configuration information, see the
Ethernet Card Software Feature and Configuration Guide for the Cisco ONS 15454, Cisco ONS 15454
SDH, and Cisco ONS 15327.
Figure 5-5 shows the card faceplate and block diagram.
Caution Shielded twisted-pair cabling should be used for inter-building applications.
Figure 5-5 ML100T-12 Faceplate and Block Diagram
ML-Series cards feature two SDH virtual ports with a maximum combined bandwidth of VC4-16c. Each
port carries an STM concatenated circuit (CCAT) with a size of VC3, VC4, VC4-2c, VC4-3c, VC4-4c,
and VC4-8c. To configure an ML-Series card SDH STM circuit, refer to the “Create Circuits and
Low-Order Tunnels” chapter of the Cisco ONS 15454 SDH Procedure Guide.
The ML-Series packet-over-SDH (POS) ports supports virtual concatenation (VCAT) of SONET/SDH
circuits and a software link capacity adjustment scheme (SW-LCAS). The ML-Series card supports a
maximum of two VCAT groups with each group corresponding to one of the POS ports. Each VCAT
group must be provisioned with two circuit members. An ML-Series card supports VC-3-2v, VC-4-2v
and VC-4-4c-2v. To configure an ML-Series card SDH VCAT circuit, refer to the “Create Circuits and
Low-Order Tunnels” chapter of the Cisco ONS 15454 SDH Procedure Guide.
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ACT
FAIL
ML100T
12
134621
0
DOS
FPGA
BTC192
port
1
4xMag.
12 x
RJ45
Octal
PHY
port
0
SMII RGGI
Octal
PHY
4xMag.
4xMag.
4
6
port
A
port
B
port
3
port
2
port
0
port
1
ch0-1 ch4-5
6
RGGI
SCL
B
a
c
k
p
l
a
n
e
BPIA
Main
Rx
BPIA
Protect
Rx
BPIA
Main
Tx
BPIA
Protect
Tx
Processor
Daughter Card
128MB SDRAM
16MB FLASH
8KB NVRAM
Packet
Buffer
6MB
Packet
Buffer
6MB
Packet
Buffer
4MB
4
2
2
4
4
2
2
Control Mem
2MB
Control Mem
2MB
Result Mem
2MB