Technical data

TraverseEdge 2020 Applications and Engineering Guide, Chapter 8: Node Synchronization
Page 8-4 Turin Networks Release 5.0.x
Internal Timing Reference
The internal timing reference generated by the TE-2020 system is rated at Stratum 3 quality. All clock per-
formance characteristics are measured at the synchronous outputs (e.g. OC-n outputs) of the TE-2020.
8.2.1 Clock Modes
Clock modes are different from timing modes as described above. Timing modes define what a clock is
referenced to, while clock modes define a state of the clock. The user usually provisions timing modes,
while clock modes are selected automatically by the system based on the state of the references. These
modes are briefly described as follows:
Normal Mode: In normal mode, the clock is externally timed, or synchronized to an external ref-
erence source. The output frequency of the clock is the same as the input reference frequency over
the long term, and the phase difference between the input and the output is bounded. It is intended
that all clocks (except Stratum 1) operate in this mode except under the failure condition of loss of
all reference input signals.
Holdover Mode: The holdover mode is the operating condition of a clock which has lost its previ-
ously-connected reference sources and is using data acquired during the normal mode to control its
output signal.
Free-run Mode: The free-run mode of a clock is its operating condition when the output signal is
totally internally controlled, with no influence of a present or previous external reference.
The clock automatically recovers from holdover (or free-run) to its original or alternate reference input
port when a suitable input signal is available. When the clock mode changes from normal (to any other
mode) the system initiates an alarm. A configurable option to disable alarms associated with the free-run
mode is provided. Information on the current operating mode of the clock is available as an “on-demand”
report.
8.2.2 Timing Reference - Input Tolerance
GR-1244-CORE allows for flexibility in determining when the TE-2020 should consider an input timing
reference failed. The TE-2020 may consider a reference failed as soon as it detects an LOS, AIS, OOF, or
LOF defect, or it may wait for several seconds up to the point when a failure is declared, to see if the defect
persists. If the TE-2020 does wait to see if the defect persists, its output synchronization performance is not
degraded.
8.2.3 Timing Distribution
The TE-2020 distributes SONET-based synchronization signals using DS1 signals derived from a termi-
nating OC-n on the TE-2020 Main Shelf. The TE-2020 can distribute the timing reference signals via:
• derived DS1 signals
• any of its OC-n interfaces