Universal Broadband Router Hardware Installation Guide

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Cisco uBR10012 Universal Broadband Router Hardware Installation Guide
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Chapter 1 Cisco uBR10012 Universal Broadband Router Overview
Cisco uBR10012 Universal Broadband Router Modules
combination of a general purpose RISC processor with advanced programmable PXF network
processors provides the capacity to support the aggregation of thousands of active connections in a single
Cisco
uBR10012 chassis when supporting IP applications such as access policy filtering, rate-based
queuing, and QoS.
PRE2 Modules
PRE2 modules are designed to address Internet service provider (ISP) requirements. The PRE2 has four
PFX network processors (containing 64 individual processors) with two independent 32-MB SDRAM
control memories on each processor set. The PRE2 provides 6.2 Mpps of processing power and has a
500-MHz RM 7000 mips processor with integrated 16-KB data and 16-KB instruction Level 1 caches,
an integrated 256-KB Level 2 cache, and a 4-MB Level 3 cache.
Cisco IOS Release 12.3(9a)BC automatically enables the following features:
• Route Processor Redundancy Plus (RPR+)
• 6.2 mpps processing power
• Software features available with PRE2 and Cisco IOS Release 12.3(9a)BC:
– EtherChannel
– TLS 802.1q
– NetFlow
PRE4 Modules
The Performance Routing Engine 4 (PRE4) is the fifth-generation Parallel Express Forwarding (PXF)
packet processing and scheduling engine for the Cisco
uBR10012 router.
PRE4 enhances the performance capability of the Cisco uBR10012 router to 10 Mpps by providing
increased density Gigabit Ethernet (GE) and higher throughput of the 10GE SPA interface.
The PRE4 runs Cisco IOS Release 12.2(33)SCB and later releases. Benefits of the PRE4 include:
• 800-MHz dual processor
• 64 PXF network processors arranged as 8 columns and 8 rows
• 512-MB packet buffer and 128-MB control memory with error-correcting code
• 4-GB ECC-protected Route Processor (RP) memory
• 10 million packets per second (Mpps) forwarding performance through the PXF complex
• 5.6-Gbps backplane bandwidth for each full-height backplane slot
• 11.2 Gbps backplane bandwidth to each SPA interface processor (SIP)
• Maximum transmission unit (MTU) support of 9216 bytes
• An external CompactFlash Disk slot (disk0)
• A 100/1000 Megabit Ethernet interface for communication between redundant PRE4s
Note Unless otherwise indicated, all references in this document to the PRE refer to the PRE, the PRE1, the
PRE2, or the PRE4 modules. The PRE is now end-of-life (EOL) and is replaced by the PRE1, PRE2, or
PRE4.