Cisco 1600 Series Router Architecture
Cisco 1600 Series Router Architecture Table of Contents Cisco 1600 Series Router Architecture............................................................................................................1 Introduction.............................................................................................................................................1 Hardware Overview................................................................................................................................
Cisco 1600 Series Router Architecture Introduction Hardware Overview Block Diagram Memory Details Boot Sequence Packet Switching Related Information Introduction This document is an overview of the hardware and software architecture of the Cisco 1600 Series Routers.
Figure 4: Cisco 1604 and 1604R Rear Panel Figure 5: Cisco 1605R Rear Panel The Cisco 1600 series routers are either run−from−Flash or run−from−RAM models. Router model names with an R are run−from−RAM routers; all other models are run−from−Flash. A more detailed description of these two memory architectures are described in Cisco 1600 Series Memory Architecture and Comparison of Cisco 1601−Cisco 1604, and Cisco 1605−R.
Non−Volatile RAM (NVRAM), PCMCIA Flash, and WIC. ♦ Input/Output (I/O) Buses allow the M68360 to individually control other devices through the SCCs. These include Universal Asynchronous Receiver/Transmitter (UART), the Ethernet controller, and the WAN port interface. • UART is an SCC integrated on the M68360. It provides the necessary user interface. It has one RS232 port, and a data communications equipment (DCE) (console) RJ45. Note: UART has no Auxiliary (data terminal equipment − DTE) port.
Module − SIMM (72−pin, 60 ns, with or without parity). If SIMM is non−parity, total DRAM can be up to 18 MB. If SIMM is with parity, total DRAM can be up to 16 MB (on−board 2 MB will be disabled). Note: The Cisco 1605−R Series Router has 8 MB on−board. Therefore, total DRAM can be up to 24 MB on that router. For more information, see Comparison of Cisco 1601, Cisco 1604, and Cisco 1605−R Memory Architectures.
Bridging software. X.25 software, Version 3.0.0. Basic Rate ISDN software, Version 1.1. 1 Ethernet/IEEE 802.3 interface(s) 1 Serial(sync/async) network interface(s) 1 ISDN Basic Rate interface(s) System/IO memory with parity disabled 2048K bytes of DRAM onboard 16384K bytes of DRAM on SIMM System running from FLASH 7K bytes of non−volatile configuration memory.
example: boot system flash slot0:c1600−sy−l.122−1a.bin This forces the RxBoot to look for the file "c1600−sy−l.122−1a.bin" on the Flash device called "slot0:". The boot system directive in the router configuration file overrides the configuration register. If there is no boot system statement, and if the configuration register is at its default value, then the RxBoot grabs the first file it finds in its Flash. If that fails, it tries to load an image from boot ROM. 3.
as set forth in subparagraph (c) of the Commercial Computer Software − Restricted Rights clause at FAR sec. 52.227−19 and subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS sec. 252.227−7013. cisco Systems, Inc. 170 West Tasman Drive San Jose, California 95134−1706 Cisco Internetwork Operating System Software IOS (tm) 1600 Software (C1600−SY−L), Version 12.1(7), RELEASE SOFTWARE (fc1) Copyright (c) 1986−2001 by cisco Systems, Inc.
Cisco IOS software creates these rings on behalf of the media controllers and then manages them jointly with the controllers. Each interface has a pair of rings: a receive (RX) ring for receiving packets and a transmit (TX) ring for transmitting packets. Receive rings have a constant number of packet buffers allocated to them that equals the size of the ring.
Step 1: The interface media controller detects a packet on the network media and copies it into a buffer pointed to by the first free element in the receive ring. Media controllers use the Direct Memory Access (DMA) method to copy packet data into memory. Step 2: The media controller changes ownership of the packet buffer back to the processor and issues a receive interrupt to the processor.
switching. The packet goes in the queue of the appropriate process (for instance, an IP packet is placed in the queue for the IP Input process), and the receive interrupt is dismissed. Step 7: Eventually the packet switching process runs, switching the packet and rewriting the MAC header as needed. Note that the packet still has not moved from the buffer it was originally copied into. After the packet is switched, the Cisco IOS software continues to the packet transmit stage.
• Maximum Number of Interfaces and Subinterfaces for Cisco IOS Platforms: IDB Limits • Product Catalog All contents are Copyright © 1992−−2002 Cisco Systems Inc. All rights reserved. Important Notices and Privacy Statement.
