Manual
Rev. 2.1 34
CobraNet™ EV-2
1 2 34
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CobraNet (TM) Evaluation Board - Optional VCXO and clock buffers.
E
2500 55th Street
Suite 210
Title:
File: EV2_VCXO.Sch
6919-Oct-2004Date: Sheet of
Engineer: Bill Lowe
www.peakaudio.com www.cirrus.com
Size: Number: Revision:A
Cirrus Logic, Inc.
Boulder, CO 80301
GND
C606
.1S
FS512_OUT
FS512_IN
VC
1
OUT
3
GND
2
VCC
4
U600
24.576MHZ VCXO
B600
.1S
GND
R606
10KP1S
GND
VCC_+3
VCC_+3
1
2
3
U601A
74LVX86S
4
5
6
U601B
74LVX86S
9
10
8
U601C
74LVX86S
12
13
11
U601D
74LVX86S
VCC
14
GND
7
U601E
74LVX86S
GND
FS512_EV
GND
VCC_+3
B601
.1S
GND
VCC_+3
FS512_IN
FS512_OUT
R603
464P1S
SSI_CLK
FS1_OUT
2 3
1
U510A
74LVX125A
12 11
13
U510D
74LVX125A
5 6
4
U510B
74LVX125A
SSI_CLK_IN SSI_CLK9 8
10
U510C
74LVX125A
AES_BCLK
AES_BCLK
FS1_IN
AES_FS1
FS1_OUT
AES_FS1
B500
.1S
VCC_+3
GND
GND
GND
GND
GND
VCC
14
GND
7
U501E
74LVX125A
2 3
1
U501A
74LVX125A
12 11
13
U501D
74LVX125A
VCC_+3
GND
GND
B501
.1S
GND
FS512_CLK
FS512_CLK
MCLK
MCLK
VCC
14
GND
7
U510E
74LVX125A
SSI_CLK_IN
FS1_IN
Clock buffers
Clock buffers
Optional VCXO
The VCXO circuit provides an example of a circuit that will reduce jitter on the
master clock. In the EV-2 application jitter is low enough where this circuit does
not improve the jitter performance significantly. The end user, because of long
trace lengths or running the master clock through other components such as gates
or FPGAs, may want to consider implementing a jitter attenuation circuit such as
this one.
Without VCXO populate R501 and not R602.
With VCXO populate R602 and not R501.
R511
51.1P1S
R512
51.1P1S
R515
51.1P1S
R514
51.1P1S
R502
51.1P1S
R503
51.1P1S
R602
51.1P1S
R501
51.1P1S