Manual

CobraNet™ EV-2
29 Rev. 2.1
1 2 34
A B C D
4
321
D
C B A
CobraNet (TM) Evaluation Board
E
2500 55th Street Suite 210
Title:
File: EV2_Main.Sch
1919-Oct-2004Date: Sheet of
Engineer: Bill Lowe
www.peakaudio.com www.cirrus.com
Size: Number: Revision:A
Cirrus Logic, Inc.
Boulder, CO 80301
MCLK SSI_CLK FS1_OUT
AD_DATA1
HPF# EN_96K AD_RESET#
A/D Converter EV2_AD.sch
AD[0..7]
HACK#HREQ#
WR#MRESET
WATCHDOG MUTE#
TXDRXD
ALE RD#
A[8..15]
INIT_IO#
MCU_P35
PROGRAM#
A[0..7]
MCU_CLK
MCU_P17
UPC and logic EV2_8051.sch
FS1_OUT
AD_DATA1
DA_RESET# DA_DATA MCLK SSI_CLK FS1_OUT EN_96K DA_CCLK DA_CS#
DA_CDOUT
D/A Converter EV2_DA.sch
DA_RESET# DA_DATA MCLK
HACK# HREQ# HCS# HRW A[0..2] AD[0..7]
MRESET
MRESET#
RSVD[1..4] MUTE# TXD RXD HRESET# SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3
SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3
WATCHDOG
FS512_IN AUX_POWER[0..3]
SCI_CLK
HEN#
ADDR3
FS512_OUT
SSI_CLK_IN
FS1_IN
Common components EV2_com.sch
HCS#
HREQ#
HWR# HACK# A[0..2] AD[0..7]
HRESET# HCS#
MRESET MRESET#
MUTE#
AD[0..7]
HREQ# HACK#
WR#
RSVD[1..4]
MRESET
MUTE#
HPF#
HPF# TXD
DA_DATA
FS1_OUT HRESET# SSI_CLK SSI_CLK
SSI_CLK
SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3
SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3
WATCHDOG
WATCHDOG
DA_RESET# FS1_OUT
FS512_IN
AUX_POWER[0..3]
SCI_CLK
AD_DATA1
SSI_DOUT[0..3] SSI_DIN[0..3]
FS512_OUTFS512_IN
SSI_CLK_IN FS1_IN
SSI_CLK
FS1_OUT
AES_BCLK
AES_FS1
FS512_CLK
MCLK
Auxiliary VXCO EV2_VCXO.sch
FS512_IN
FS512_OUT FS512_CLK
HEN#
HEN#
RESET# AES_DOUT AES_BCLK AES_WCLK
AES_DIN
EN_96K# EN_96K FS512_OUT
AES I/O EV2_AES.Sch
MRESET#
EN_96K#
AES_DIN
AES_DIN AES_DOUT AES_DOUT
AUX_POWER[0..3]
SCI_CLK Power EV2_pwr.sch
AES_FS1 AES_BCLK
AES_FS1 AES_BCLK
EN_96K
AD[0..7] WR#
PROGRAM#
INIT_IO#
HPF#
AUX_POWER[0..3] ALE SCI_CLK A[8..15] RSVD[1..4] SSI_DOUT[0..3] SSI_DIN[0..3] AD_DATA1
DA_DATA
AES_DIN AES_DOUT MUTE# RD#
HCS#
HEN#
DA_RESET#
HRESET#
MCU_P35 FS512_CLK FS1_OUT MCU_CLK AES_BCLK
HWR#
A[0..7]
ADDR3
AD_RESET#
DA_CDOUT DA_CCLK
DA_CS#
MCU_P17
EN_96K
EN_96K#
CNEV_FPGA EV2_FPGA.Sch
AD[0..7]
RXD
TXD
WR#
ALE
ALE A[8..15]
RD#
RD#
PROGRAM# INIT_IO#
INIT_IO# PROGRAM#
A[8..15]
MUTE# MCU_P35MCU_P35 RSVD[1..4] FS512_CLK FS1_OUT MCU_CLK
RXD
AES_BCLK
HWR#
A[0..7]
A[0..7]
MCLK ADDR3
ADDR3
EN_96K
AD_RESET#
AD_RESET#
EN_96K
MCU_CLK
MCLK
FS512_OUT
DA_CCLK
DA_CDOUT
DA_CS#
DA_CCLKDA_CDOUT DA_CS#
MCU_P17
MCU_P17 EN_96K
EN_96K#
FS512_OUT
SSI_CLK_IN
SSI_CLK_IN
FS1_IN
FS1_IN
Appendix D: EV-2 Schematic Drawings