Manual

Rev. 2.1 16
CobraNet™ EV-2
Memory
Location
R/W Description
0x8000 W Bit register for green LED, CR903. 0=LED on, 1=LED off.
Refer to Table 10 on page 20 for this and other LED regis-
ters.
0x8001 W Bit register for red LED, CR904. 0=LED on, 1=LED off.
0x8002 W Bit register for yellow LED, CR905. 0=LED on, 1=LED off.
0x8004 W Bit register for green LED blink control. 0=blink off, 1=blink
on.
0x8005 W Bit register for green LED blink control. 0=blink off, 1=blink
on.
0x8006 W Bit register for green LED blink control. 0=blink off, 1=blink
on.
0x8008 W DAC audio routing address (see Table 7 on page 18).
0x8009 W Bit register for DAC mute signal. 0=mute on, 1=mute off.
0x800A W Bit register for sample rate mode. 0=48k, 1=96k. Note: use
AD1 instead of AD0
0x800B W Bit register for DAC reset signal. 0=reset on, 1=reset off.
0x8010 R Audio Calibration Status. 1=Calibrating, 0=Ready. See the
Calibrating Audio section for details.
0x8010 W Manual ADC Calibration. 0=Normal, 1=Calibrate. See the
Calibrating the ADC section for details. (Rev. D applicable
only)
0x8011 W Bit register for ADC slave/master control. 0=Slave, 1=Mas-
ter. (Rev. D applicable only)
0x8012 W ADC high pass filter (HPF) select. 0=Enabled, 1=Disabled.
0x8018 W AES3 audio routing address (see Table 7 on page 18).
0x8019 W Bit register for AES3 mute signal. 0=AES output muted,
1=Unmuted.
0x8020 W SSI 0 audio routing address (see Table 7 on page 18).
0x8021 W Bit register for SSI 0 mute signal. 0=Muted, 1=Unmuted.
0x8028 W SSI 1 audio routing address (see Table 7 on page 18).
0x8029 W Bit register for SSI 1 mute signal. 0=Muted, 1=Unmuted.
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration