Owner's manual

21-4 DS785UM1
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
2
1
2
1
21
these two words will occupy positions 0 and 1 in the FIFO. The FIFO now contains one
complete left / right stereo sample. The words written by the programmer must always
be right justified when writing 16-bit and 24-bit values.
If the programmer writes another left and right stereo sample to the I2STX0Lft and
I2STX0Rt registers respectively, these words are loaded into the FIFO and will occupy
positions 2 and 3. Subsequent writes will fill positions 4 and 5 and so on. The FIFO full
flag is set when all 8 FIFO locations are filled by left / right sample pairs.
If an attempt is made to write another left / right stereo pair to the FIFO while it is full,
the new samples are ignored and the FIFO overflow flag is set. (See “Register
Descriptions” on page 448 on clearing this flag.) None of the existing FIFO locations are
overwritten.
3. Enable the I
2
S transmit channel
Once the FIFO has been loaded, the channel enable I2STX0En one-bit register (see
“I
2
S TX Register Descriptions” on page 21-13) is set. At this point, both the left and right
stereo data from the 1st FIFO location are read by the I
2
S controller and copied into
separate left and right holding registers. The left holding register is parallel loaded into a
shift register and is serially shifted out the I
2
S sdo0 data line. This shifting out process is
timed on the I
2
S audio word and bit clock. Once the left sample is shifted out, the right
holding register is parallel loaded into the shift register and is serially shifted out the I
2
S
sdo0 line.
If the I
2
S controller is programmed to transmit 16 or 24 bit words, the lower 16 or 24 bits
are taken from the holding registers and loaded into the shift register. The upper bits are
ignored by the I
2
S controller.
When the right sample is loaded into the shift register, the I
2
S controller reads the next left
and right stereo samples from the 2
nd
FIFO location. After these have been loaded into the
shift register in the same manner as above, FIFO location 3 is read and so on. After samples
15 and 16 (FIFO location 7) are taken from the FIFO, the FIFO read pointer will wrap around
to location 0 and continue as before as long as the channel is enabled. If the I
2
S controller is
disabled at any point, all FIFO locations are zeroed and the FIFO write and read pointers are
reset.
If the transmit channel corresponding to the FIFO is disabled, the I
2
S controller will stop
transmitting the current sample that is in the shift register. The data in the FIFO is not touched
and the FIFO read and write pointers stay as they are. Upon re-enabling the channel, the I
2
S
controller will advance the FIFO pointer, read the left and right stereo samples, and transmit
them. The effect of this is that the data currently residing in the holding registers at the time
the channel is disabled is lost.
To end transmission of data completely while there is data in the FIFO, first disable the
corresponding channel. This action will ensure that the channels state machines are reset.
The next step should be to disable the I
2
S controller, which will result in the FIFO’s being
reset. Any samples currently in the FIFO will be lost as a result.