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Table Of Contents

Contents
- Figures
- Tables
- Revision History
Preface
- P.1 About the EP93xx User’s Guide
- P.2 Related Documents from Cirrus Logic
- P.3 Reference Documents
- P.4 Notational Conventions
- P.5 Register Example
Introduction
- 1.1 Introduction
- 1.2 EP93xx Features
- 1.3 EP93xx Processor Applications
- 1.4 EP93xx Processor Highlights
ARM920T Core and Advanced High-Speed Bus (AHB)
- 2.1 Introduction
- 2.2 Overview: ARM920T Core
- 2.3 AHB Decoder
MaverickCrunch Co-Processor
- 3.1 Introduction
- 3.2 Programming Examples
  - 3.2.1 Example 1
  - 3.2.2 Example 2
    - 3.2.2.1 C Code
    - 3.2.2.2 MaverickCrunch Assembly Language Instructions
- 3.3 DSPSC Register
- 3.4 ARM Co-Processor Instruction Format
- 3.5 Instruction Set for the MaverickCrunch Co-Processor
Boot ROM
- 4.1 Introduction
  - 4.1.1 Boot ROM Hardware Operational Overview
    - 4.1.1.1 Memory Map
  - 4.1.2 Boot ROM Software Operational Overview
- 4.2 Boot Options
System Controller
- 5.1 Introduction
- 5.2 Registers
Vectored Interrupt Controller
- 6.1 Introduction
- 6.2 Registers
Raster Engine With Analog/LCD Integrated Timing and Interface
- 7.1 Introduction
- 7.2 Features
- 7.3 Raster Engine Features Overview
- 7.4 Functional Details
- 7.5 Registers
Graphics Accelerator
- 8.1 Overview
- 8.2 Block Processing Modes
- 8.3 Line Draws
  - 8.3.1 Breshenham Line Draws
  - 8.3.2 Pixel Step Line Draws
- 8.4 Memory Organization for Graphics Accelerator
- 8.5 Register Programming
  - 8.5.1 Word Count
    - 8.5.1.1 Example: 8 BPP mode
    - 8.5.1.2 Example: 24 BPP (packed) mode
  - 8.5.2 Pixel End and Start
- 8.6 Register Usage
- 8.7 Registers
1/10/100 Mbps Ethernet LAN Controller
- 9.1 Introduction
- 9.2 Descriptor Processor
- 9.3 Registers
DMA Controller
- 10.1 Introduction
- 10.2 Registers
  - 10.2.1 DMA Controller Memory Map
  - 10.2.2 Internal M2P/P2M Channel Register Map
Universal Serial Bus Host Controller
- 11.1 Introduction
  - 11.1.1 Features
- 11.2 Overview
- 11.3 Registers
Static Memory Controller
- 12.1 Introduction
- 12.2 Static Memory Controller Operation
- 12.3 PCMCIA Interface (EP9315 Processor Only)
- 12.4 PC Card Memory-Mode Enable Signals
- 12.5 PC Card Memory Mapping
- 12.6 Registers
  - 12.6.1 Bank Configuration Registers
  - 12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only)
SDRAM, SyncROM, and SyncFLASH Controller
- 13.1 Introduction
- 13.2 Booting from SyncROM or SyncFLASH
- 13.3 Address Pin Usage
- 13.4 SDRAM Initialization
- 13.5 Programming Mode Register: SDRAM Or SyncROM Device
- 13.6 SDRAM Self Refresh
  - 13.6.1 Entering Self Refresh Mode
  - 13.6.2 Exiting Self Refresh Mode
- 13.7 Programming Registers: SyncFLASH Device
- 13.8 External Synchronous Memory System
  - 13.8.1 Chip Select SDCSN[3:0] Decoding
  - 13.8.2 Address/Data/Control Required by Memory System
- 13.9 Registers
UART1 With HDLC and Modem Control Signals
- 14.1 Introduction
- 14.2 UART Overview
- 14.3 Modem
- 14.4 HDLC
- 14.5 UART1 Package Dependency
  - 14.5.1 Clocking Requirements
  - 14.5.2 Bus Bandwidth Requirements
- 14.1 Registers
UART2
- 15.1 Introduction
- 15.2 IrDA SIR Block
- 15.3 UART2 Package Dependency
  - 15.3.1 Clocking Requirements
  - 15.3.2 Bus Bandwidth Requirements
- 15.4 Registers
UART3 With HDLC Encoder
- 16.1 Introduction
- 16.2 Implementation Details
- 16.3 Registers
IrDA
- 17.1 Introduction
- 17.2 IrDA Interfaces
- 17.3 Shared IrDA Interface Feature
- 17.4 Medium IrDA Specific Features
  - 17.4.1 Introduction
    - 17.4.1.1 Bit Encoding
    - 17.4.1.2 Frame Format
  - 17.4.2 Functional Description
- 17.5 Fast IrDA Specific Features
- 17.6 Registers
Timers
- 18.1 Introduction
- 18.2 Registers
Watchdog Timer
- 19.1 Introduction
- 19.1 Registers
Real Time Clock With Software Trim
- 20.1 Introduction
  - 20.1.1 Software Trim
  - 20.1.2 Reset Control
- 20.1 Registers
I2S Controller
- 21.1 Introduction
- 21.2 I2S Transmitter Channel Overview
- 21.3 I2S Receiver Channel Overview
  - 21.3.1 Receiver FIFO’s
- 21.4 I2S Master Clock Generation
- 21.5 I2S Bit Clock Rate Generation
  - 21.5.1 Example of the Bit Clock Generation.
  - 21.5.2 Example of Right Justified LRCK format
- 21.6 Interrupts
- 21.7 Registers
AC’97 Controller
- 22.1 Introduction
- 22.2 Interrupts
  - 22.2.1 Channel Interrupts
  - 22.2.2 Global Interrupts
- 22.3 System Loopback Testing
- 22.4 Registers
Synchronous Serial Port
- 23.1 Introduction
- 23.2 Features
- 23.3 SSP Functionality
- 23.4 SSP Pin Multiplex
- 23.5 Configuring the SSP
- 23.6 Registers
Pulse Width Modulator
- 24.1 Introduction
- 24.2 Theory of Operation
  - 24.2.1 PWM Programming Examples
  - 24.2.2 Programming Rules
- 24.3 Registers
Analog Touch Screen Interface
- 25.1 Introduction
- 25.2 Touch Screen Controller Operation
- 25.3 Registers
Keypad Interface
- 26.1 Introduction
- 26.2 Theory of Operation
- 26.3 Registers
IDE Interface
- 27.1 Introduction
- 27.2 Theory of Operation
- 27.3 Registers
GPIO Interface
- 28.1 Introduction
- 28.2 Registers
Security
- 29.1 Introduction
- 29.2 Features
- 29.3 Contact Information
- 29.4 Registers
Glossary
EP93XX Register List

DS785UM1 17-37

IrDA

EP93xx User’s Guide

RFC: RFC mask bit. When high, the FIR RFC status can

generate an interrupt.

RFS: RFS mask bit. When high, the FIR RFS status can

generate an interrupt.

TAB: TAB mask bit. When high, the FIR TAB status can

generate an interrupt.

TFC: TFC mask bit. When high, the FIR TFC status can

generate an interrupt.

TFS: TFS mask bit. When high, the FIR TFS status can

generate an interrupt.

FIIR

Address:

0x808B_0188 - Read Only

Default:

0x0000_0000

Definition:

FIR Interrupt Register. An interrupt is signalled from this block if any bit is high

in the FIIR.

Bit Descriptions:

RSVD: Reserved. Unknown During Read.

RFL: Logical AND of FIR RFL status bit and RFL mask bit.

RIL: Logical AND of FIR RIL status bit and RIL mask bit.

RFC: Logical AND of FIR RFC status bit and RFC mask bit.

RFS: Logical AND of FIR RFS status bit and RFS mask bit.

TAB: Logical AND of FIR TAB status bit and TAB mask bit.

TFC: Logical AND of FIR TFC status bit and TFC mask bit.

TFS: Logical AND of FIR TFS status bit and TFS mask bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

1514131211109876543210

RSVD RFL RIL RFC RFS TAB TFC TFS