Owner's manual

14-4 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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14.2.1.4 Baud Rate Generator
The baud rate generator contains free-running counters which generate the internal x16
clocks and the Baud16 signal. Baud16 provides timing information for UART transmit and
receive control. Baud16 is a stream of pulses with a width of one UARTCLK clock period and
a frequency of sixteen times the baud rate.
14.2.1.5 Transmit FIFO
The transmit FIFO is an 8-bit wide, 16-entry deep, first-in, first-out memory buffer. CPU data
written across the APB interface and data written across the DMA interface is stored in the
FIFO until read out by the transmit logic. The transmit FIFO can be disabled to act as a one-
byte holding register.
14.2.1.6 Receive FIFO
The receive FIFO is an 11 bit wide, 16-entry deep, FIFO memory buffer. Received data, and
corresponding error bits, are stored in the receive FIFO by the receive logic until read out by
the CPU across the APB interface or across the DMA interface. The FIFO can be disabled to
act as a one-byte holding register.
14.2.1.7 Transmit Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit
FIFO. Control logic outputs the serial bit stream beginning with a start bit, data bits, least
significant bit (LSB) first, followed by parity bit, and then stop bits according to the
programmed configuration in control registers.
14.2.1.8 Receive Logic
The receive logic performs serial-to-parallel conversion on the received bit stream after a
valid start pulse has been detected. Parity, frame error checking and line break detection are
also performed, and the data with associated parity, framing and break error bits is written to
the receive FIFO.
14.2.1.9 Interrupt Generation Logic
Four individual maskable active HIGH interrupts are generated by the UART, and a combined
interrupt output is also generated as an OR function of the individual interrupt requests.
The single combined UART interrupt (UARTINTR) is routed to the system interrupt controller.
In addition, a separate receive FIFO interrupt UARTRXINTR and a transmit FIFO interrupt
UARTTXINTR are routed to the system interrupt controller. (See Chapter 6,, “Vectored
Interrupt Controller” on page 6-1 for additional details.) Separate receive and transmit FIFO
status signals indicate to the DMA interface when there is room in the transmit FIFO for more
data and when there is data in the receive FIFO.