Owner's manual
Table Of Contents
- Contents
- Preface
- Introduction
- 1.1 Introduction
- 1.2 EP93xx Features
- 1.3 EP93xx Processor Applications
- 1.4 EP93xx Processor Highlights
- 1.4.1 High-Performance ARM920T Core
- 1.4.2 MaverickCrunch™ Co-processor for Ultra-Fast Math Processing
- 1.4.3 MaverickKey™ Unique ID Secures Digital Content in OEM Designs
- 1.4.4 Integrated Multi-Port USB 2.0 Full Speed Hosts with Transceivers
- 1.4.5 Integrated Ethernet MAC Reduces BOM Costs
- 1.4.6 8x8 Keypad Interface Reduces BOM Costs
- 1.4.7 Multiple Booting Mechanisms Increase Flexibility
- 1.4.8 Abundant General Purpose I/Os Build Flexible Systems
- 1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)
- 1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated Touch-Screen Interface or General ADC Functionality
- 1.4.11 Raster Analog / LCD Controller
- 1.4.12 Graphics Accelerator
- 1.4.13 PCMCIA Interface
- ARM920T Core and Advanced High-Speed Bus (AHB)
- MaverickCrunch Co-Processor
- 3.1 Introduction
- 3.2 Programming Examples
- 3.3 DSPSC Register
- 3.4 ARM Co-Processor Instruction Format
- 3.5 Instruction Set for the MaverickCrunch Co-Processor
- 3.5.1 Load and Store Instructions
- 3.5.2 Move Instructions
- 3.5.3 Accumulator and DSPSC Move Instructions
- 3.5.4 Copy and Conversion Instructions
- 3.5.5 Shift Instructions
- 3.5.6 Compare Instructions
- 3.5.7 Floating Point Arithmetic Instructions
- 3.5.8 Integer Arithmetic Instructions
- 3.5.9 Accumulator Arithmetic Instructions
- Boot ROM
- System Controller
- Vectored Interrupt Controller
- Raster Engine With Analog/LCD Integrated Timing and Interface
- 7.1 Introduction
- 7.2 Features
- 7.3 Raster Engine Features Overview
- 7.4 Functional Details
- 7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface)
- 7.4.2 Video FIFO
- 7.4.3 Video Pixel MUX
- 7.4.4 Blink Function
- 7.4.5 Color Look-Up-Tables
- 7.4.6 Color RGB Mux
- 7.4.7 Pixel Shift Logic
- 7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays
- 7.4.9 Hardware Cursor
- 7.4.10 Video Timing
- 7.4.11 Blink Logic
- 7.4.12 Color Mode Definition
- 7.5 Registers
- Graphics Accelerator
- 1/10/100 Mbps Ethernet LAN Controller
- 9.1 Introduction
- 9.2 Descriptor Processor
- 9.2.1 Receive Descriptor Processor Queues
- 9.2.2 Receive Descriptor Queue
- 9.2.3 Receive Status Queue
- 9.2.3.1 Receive Status Format
- 9.2.3.2 Receive Flow
- 9.2.3.3 Receive Errors
- 9.2.3.4 Receive Descriptor Data/Status Flow
- 9.2.3.5 Receive Descriptor Example
- 9.2.3.6 Receive Frame Pre-Processing
- 9.2.3.7 Transmit Descriptor Processor Queues
- 9.2.3.8 Transmit Descriptor Queue
- 9.2.3.9 Transmit Descriptor Format
- 9.2.3.10 Transmit Status Queue
- 9.2.3.11 Transmit Status Format
- 9.2.3.12 Transmit Flow
- 9.2.3.13 Transmit Errors
- 9.2.3.14 Transmit Descriptor Data/Status Flow
- 9.2.4 Interrupts
- 9.2.5 Initialization
- 9.3 Registers
- DMA Controller
- 10.1 Introduction
- 10.1.1 DMA Features List
- 10.1.2 Managing Data Transfers Using a DMA Channel
- 10.1.3 DMA Operations
- 10.1.4 Internal M2P or P2M AHB Master Interface Functional Description
- 10.1.5 M2M AHB Master Interface Functional Description
- 10.1.6 AHB Slave Interface Limitations
- 10.1.7 Interrupt Interface
- 10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description
- 10.1.9 Internal M2P/P2M DMA Functional Description
- 10.1.10 M2M DMA Functional Description
- 10.1.11 DMA Data Transfer Size Determination
- 10.1.12 Buffer Descriptors
- 10.1.13 Bus Arbitration
- 10.2 Registers
- 10.1 Introduction
- Universal Serial Bus Host Controller
- Static Memory Controller
- SDRAM, SyncROM, and SyncFLASH Controller
- UART1 With HDLC and Modem Control Signals
- UART2
- UART3 With HDLC Encoder
- IrDA
- Timers
- Watchdog Timer
- Real Time Clock With Software Trim
- I2S Controller
- AC’97 Controller
- Synchronous Serial Port
- 23.1 Introduction
- 23.2 Features
- 23.3 SSP Functionality
- 23.4 SSP Pin Multiplex
- 23.5 Configuring the SSP
- 23.5.1 Enabling SSP Operation
- 23.5.2 Master/Slave Mode
- 23.5.3 Serial Bit Rate Generation
- 23.5.4 Frame Format
- 23.5.5 Texas Instruments® Synchronous Serial Frame Format
- 23.5.6 Motorola® SPI Frame Format
- 23.5.7 Motorola SPI Format with SPO=0, SPH=0
- 23.5.8 Motorola SPI Format with SPO=0, SPH=1
- 23.5.9 Motorola SPI Format with SPO=1, SPH=0
- 23.5.10 Motorola SPI Format with SPO=1, SPH=1
- 23.5.11 National Semiconductor® Microwire™ Frame Format
- 23.6 Registers
- Pulse Width Modulator
- Analog Touch Screen Interface
- 25.1 Introduction
- 25.2 Touch Screen Controller Operation
- 25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation
- 25.2.2 Five-wire and Seven-wire Operation
- 25.2.3 Direct Operation
- 25.2.4 Measuring Analog Input with the Touch Screen Controls Disabled
- 25.2.5 Measuring Touch Screen Resistance
- 25.2.6 Polled and Interrupt-Driven Modes
- 25.2.7 Touch Screen Package Dependency
- 25.3 Registers
- Keypad Interface
- IDE Interface
- GPIO Interface
- Security
- Glossary
- EP93XX Register List
DS785UM1 7-13
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
Table 7-3. Output Pixel Transfer Modes
Shift
Mode
Color
Mode
Output
Mode
P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0)
0x0
0x0
0x4
0x8
single pixel
per clock up
to 24 bits
wide
R(1) R(0) G(1) G(0) B(1) B(0) R(7) R(6) R(5) R(4) R(3) R(2) G(7) G(6) G(5) G(4) G(3) G(2) B(7) B(6) B(5) B(4) B(3) B(2)
0x0 0x5
single 16-bit
565 pixel per
clock
R(3) R(2) G(5) G(4) B(3) B(2) R(4) R(3) R(2) R(1) R(0) R(4) G(5) G(4) G(3) G(2) G(1) G(0) B(4) B(3) B(2) B(1) B(0) B(4)
0x0 0x6
single 16-bit
555 pixel per
clock
R(3) R(2) G(3) G(2) B(3) P(2) R(4) R(3) R(2) R(1) R(0) R(4) G(4) G(3) G(2) G(1) G(0) G(4) B(4) B(3) B(2) B(1) B(0) B(4)
0x1
0x0
0x4
0x8
single 24-bit
pixel mapped
to 18 bits
each clk
X X X X X X R(7) R(6) R(5) R(4) R(3)
R(2)
*
G(7) G(6) G(5) G(4) G(3)
G(2)
*
B(7) B(6) B(5) B(4) B(3)
B(2)
*
0x1 0x5
single 16-bit
565 pixel
mapped to
18 bits each
clk
X X X X X X R(4) R(3) R(2) R(1) R(0)
R(4)
*
G(5) G(4) G(3) G(2) G(1)
G(0)
*
B(4) B(3) B(2) B(1) B(0)
B(4)
*
0x1 0x6
single 16-bit
555 pixel
mapped to
18 bits each
clk
X X X X X X R(4) R(3) R(2) R(1) R(0)
R(4)
*
G(4) G(3) G(2) G(1) G(0)
G(4)
*
B(4) B(3) B(2) B(1) B(0)
B(4)
*
0x2
0x0
0x8
progressive
scan
2 pixels per
shift clock
dual scan
P1(20)
R1(4)
*
P1(12)
G1(4)
*
P1(4)
B1(4)
*
P0(20)
R0(4)
*
P0(12)
G0(4)
*
P0(4)
B0(4)
*
P1(23)
R1(7)
P1(22)
G1(6)
P1(21)
G1(5)
P1(15)
G1(7)
P1(14)
G1(6)
P1(13)
G1(5)
P1(7)
B1(7)
P1(6)
B1(6)
P1(5)
B1(5)
P0(23)
R0(7)
P0(22)
R0(6)
P0(21)
R0(5)
P0(15)
G0(7)
P0(14)
G0(6)
P0(13)
G0(5)
P0(7)
B0(7)
P0(6)
B0(6)
P0(5)
B0(5)
Lower
P(20)
R(4)
*
Lower
P(12)
G(4)
*
Lower
P(4)
B(4)
*
Upper
P(20)
R(4)
*
Upper
P(12)
G(4)
*
Upper
P(4)
B(4)
*
Lower
P(23)
R(7)
Lower
P(22)
R(6)
Lower
P(21)
R(5)
Lower
P(15)
G(7)
Lower
P(14)
G(6)
Lower
P(13)
G(5)
Lower
P(7)
B(7)
Lower
P(6)
B(6)
Lower
P(5)
B(5)
Upper
P(23)
R(7)
Upper
P(22)
R(6)
Upper
P(21)
R(5)
Upper
P(15)
G(7)
Upper
P(14)
G(6)
Upper
P(13)
G(5)
Upper
P(7)
B(7)
Upper
P(6)
B(6)
Upper
P(5)
B(5)
0x3
0x0
0x8
progressive
scan
4 pixels per
shift clock
dual scan
P3(14)
G3(6)
*
P3(6)
B3(6)
*
P2(14)
B2(6)
*
P2(6)
B2(6)
*
P1(14)
G1(6)
*
P1(6)
B1(6)
*
P0(14)
G0(6)
*
P0(6)
B0(6)
*
P3(23)
R3(7)
P3(22)
R3(6)
*
P3(15)
G3(7)
P3(7)
B3(7)
P2(23)
R2(7)
P2(22)
R2(6)
*
P2(15)
G2(7)
P2(7)
B2(7)
P1(23)
R1(7)
P1(22)
R1(6)
*
P1(15)
G1(7)
P1(7)
B1(7)
P0(23)
R0(7)
P0(22)
R0(6)
*
P0(15)
G0(7)
P0(7)
B0(7)
Lower
P1(14)
G1(6)
*
Lower
P1(6)
B1(6)
*
Upper
P1(14)
G1(6)
*
Upper
P1(6)
B1(6)
*
Lower
P0(14)
G0(6)
*
Lower
P0(6)
B0(6)
*
Upper
P0(14)
G0(6)
*
Upper
P0(6)
B0(6)
*
Lower
P1(23)
R1(7)
Lower
P1(22)
R1(6)
*
Lower
P1(15)
G1(7)
Lower
P1(7)
B1(7)
Upper
P1(23)
R1(7)
Upper
P1(22)
R1(6)
*
Upper
P1(15)
G1(7)
Upper
P1(7)
B1(7)
Lower
P0(23)
R0(7)
Lower
P0(22)
R0(6)
*
Lower
P0(15)
G0(7)
Lower
P0(7)
B0(7)
Upper
P0(23)
R0(7)
Upper
P0(22)
R0(6)
*
Upper
P0(15)
G0(7)
Upper
P0(7)
B0(7)
0x4
0x0
0x8
progressive
scan
8 pixels per
shift clock
dual scan
P7(23)
R7
*
P6(23)
R6
*
P5(23)
R5
*
P4(23)
R4
*
P3(23)
R3
*
P2(23)
R2
*
P1(23)
R1
*
P0(23)
R0
*
P7(15)
G7
*
P7(7)
B7
*
P6(15)
G6
*
P6(7)
B6
*
P5(15)
G5
*
P5(7)
B5
*
P4(15)
G4
*
P4(7)
B4
*
P3(15)
G3
*
P3(7)
B3
*
P2(15)
G2
*
P2(7)
B2
*
P1(15)
G1
*
P1(7)
B1
*
P0(15)
G0
*
P0(7)
B0
*
Lower
P3(23)
R3
*
Upper
P3(23)
R3
*
Lower
P2(23)
R2
*
Upper
P2(23)
R2
*
Lower
P1(23)
R1
*
Upper
P1(23)
R1
*
Lower
P0(23)
R0
*
Upper
P0(23)
R0
*
Lower
P3(15)
G3
*
Lower
P3(7)
B3
*
Upper
P3(15)
G3
*
Upper
P3(7)
B3
*
Lower
P2(15)
G2
*
Lower
P2(7)
B2
*
Upper
P2(15)
G2
*
Upper
P2(7)
B2
*
Lower
P1(15)
G1
*
Lower
P1(7)
B1
*
Upper
P1(15)
G1
*
Upper
P1(7)
B1
*
Lower
P0(15)
G0
*
Lower
P0(7)
B0
*
Upper
P0(15)
G0
*
Upper
P0(7)
B0
*
0x5
0x0
0x8
2 2/3 pixels
per clock
XXXXXXXXXXXXXXXXG2B2R1G1B1R0G0B0
XXXXXXXXXXXXXXXXB5R4G4B4R3G3B3R2
XXXXXXXXXXXXXXXXR7G7B7R6G6B6R5G5