EP93XX ® ARM 9 Embedded Processor Family EP93xx Use r ’s Gu id e ©Copyright 2007 Cirrus Logic, Inc. http://www.cirrus.
EP93xx User’s Guide Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
EP93xx User’s Guide Contents Chapter Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiv Chapter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii Preface..............................
EP93xx User’s Guide 2.3.2 AHB-to-APB Bridge .......................................................................................................2-12 2.3.2.1 Function and Operation of the AHB-to-APB Bridge.....................................2-12 2.3.3 APB Slave .....................................................................................................................2-13 2.3.4 Register Definitions .................................................................................................
EP93xx User’s Guide 4.2.5 Synchronous Memory Operation.....................................................................................4-7 Chapter 5. System Controller ............................................................................... 5-1 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1.1 System Startup .....................................................................................
EP93xx User’s Guide 7.4.8.6 FRAME_CNTx timing ..................................................................................7-16 7.4.8.7 Grayscale Look-Up Table (GrySclLUT) .......................................................7-17 7.4.8.8 GrySclLUT Timing Diagram .........................................................................7-18 7.4.9 Hardware Cursor ...........................................................................................................7-24 7.4.9.
EP93xx User’s Guide 8.6.4 Block Copy Function......................................................................................................8-18 8.6.4.1 Example of Block Copy................................................................................8-21 8.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22 Chapter 9. 1/10/100 Mbps Ethernet LAN Controller ...........................................
EP93xx User’s Guide Chapter 10. DMA Controller................................................................................ 10-1 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 10.1.1 DMA Features List.......................................................................................................10-1 10.1.2 Managing Data Transfers Using a DMA Channel ..................................................
EP93xx User’s Guide 11.2.4 Host Controller Responsibilities...................................................................................11-8 11.2.4.1 USB States ................................................................................................11-8 11.2.4.2 Frame Management ..................................................................................11-8 11.2.4.3 List Processing ..........................................................................................11-8 11.2.
EP93xx User’s Guide 14.2.1.9 Interrupt Generation Logic .........................................................................14-4 14.2.1.10 Synchronizing Registers and Logic .........................................................14-5 14.2.2 UART Operation ..........................................................................................................14-5 14.2.2.1 Error Bits....................................................................................................14-6 14.2.2.
EP93xx User’s Guide Chapter 17. IrDA .................................................................................................. 17-1 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 17.2 IrDA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 17.3 Shared IrDA Interface Feature . . . . . . . . . . . . . . . . . . . . . .
EP93xx User’s Guide Chapter 20. Real Time Clock With Software Trim ............................................ 20-1 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 20.1.1 Software Trim ..............................................................................................................20-1 20.1.1.1 Software Compensation ............................................................................
EP93xx User’s Guide 23.5 Configuring the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2 23.5.1 Enabling SSP Operation..............................................................................................23-2 23.5.2 Master/Slave Mode......................................................................................................23-3 23.5.3 Serial Bit Rate Generation............................................................
EP93xx User’s Guide Chapter 27. IDE Interface .................................................................................... 27-1 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1 27.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1 27.2.1 Diagrams and State Machines ......................................................
EP93xx User’s Guide Figure 4-1. Flow Chart of Boot ROM Software..............................................................................................4-4 Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices ...........................................................4-7 Figure 5-1. Phase Locked Loop (PLL) Structure ...........................................................................................5-4 Figure 5-2. Clock Generation System .............................................
EP93xx User’s Guide Figure 10-4. Edge-triggered DREQ Mode .................................................................................................10-17 Figure 11-1. USB Focus Areas ...................................................................................................................11-2 Figure 11-2. Communication Channels .......................................................................................................11-3 Figure 11-3. Typical List Structure .....................
EP93xx User’s Guide Figure 25-1. Different Types of Touch Screens ..........................................................................................25-2 Figure 25-2. 8-Wire Resistive Interface Switching Diagram .......................................................................25-5 Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram............................................................25-6 Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart ............................
EP93xx User’s Guide Table 3-6. LDC/STC Opcode Map ..............................................................................................................3-16 Table 3-7. CDP Opcode Map ......................................................................................................................3-16 Table 3-8. MCR Opcode Map .....................................................................................................................3-17 Table 3-9. MRC Opcode Map .......................
EP93xx User’s Guide Table 8-2. bpp Memory Organization............................................................................................................8-5 Table 8-3. 4 bpp Memory Organization.........................................................................................................8-5 Table 8-4. 8 bpp Memory Organization.........................................................................................................8-6 Table 8-5. 16 bpp Memory Organization..................
EP93xx User’s Guide Table 11-1. Frame Bandwidth Allocation ....................................................................................................11-7 Table 11-2. OpenHCI Register Addresses................................................................................................11-11 Table 12-1. PCMCIA Address Memory Ranges..........................................................................................12-5 Table 12-2. PCMCIA Pin Usage............................................
EP93xx User’s Guide Table 17-5. UART2 / IrDA Modes .............................................................................................................17-21 Table 17-6. IrDA Service Memory Accesses / Second .............................................................................17-22 Table 18-1. Timers Register Map................................................................................................................18-2 Table 19-1. Watchdog Timer Register Memory Map .................
EP93xx User’s Guide Table 28-5. GPIO Register Address Map....................................................................................................28-9 Table 29-1. Security Register List ...............................................................................................................29-2 Table 30-1. Glossary ...................................................................................................................................30-1 Table 31-1. EP93xx Register List.........
17Preface P.1 About the EP93xx User’s Guide This EP93xx User’s Guide describes the architecture, hardware, and operation of the Cirrus Logic EP9301, EP9302, EP9307, EP9312, and EP9315 processors. It is intended to be used in conjunction with the respective EP93xx Data Sheets, which contain the full electrical specifications for the EP93xx processors. The EP9301, EP9302, EP9307, EP9312 processors are functional subsets of the EP9315 processor. All chapters in this Guide apply to the EP9315 processor.
PP Preface EP93xx User’s Guide Table P-2.
Note: “X” means Function is included; “-” means Function is not included P.2 Related Documents from Cirrus Logic P 1. EP9301 Data Sheet, Document Number - DS636PP5 2. EP9302 Data Sheet, Document Number - DS653PP3 3. EP9307 Data Sheet, Document Number - DS667PP4 4. EP9312 Data Sheet, Document Number - DS515PP7 5. EP9315 Data Sheet, Document Number - DS638PP1 P.3 Reference Documents 1. ARM®920T Technical Reference Manual, ARM Limited 2. AMBA Specification (Rev. 2.0), ARM IHI 0011A, ARM Limited 3.
PP Preface EP93xx User’s Guide • Registers are named using mixed upper and lower case alphanumeric, for example, SysCfg or PxDDR. Where there are multiple registers with the same names, a lower case “x” is used as a place holder. For example, in the PxDDR registers, x represents a letter from A to H, indicating the specific port being discussed P CAUTION:In the Internal Register Map in “Internal Register Map” on page 2-17 some memory locations are listed as Reserved.
REV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B, 2 - Rev C, 3 - Rev D. SBOOT: Serial Boot Flag. This bit is read-only. 1 hardware detected Serial Boot selection 0 hardware detected Normal Boot LCSn7, LCSn6: Latched version of CSn7 and CSn6 respectively. These are used to define the external bus width for the boot code boot. LASDO: Latched version of ASDO pin. Used to select synchronous versus asynchronous boot device. LEEDA: Latched version of EEDAT pin.
PP Preface EP93xx User’s Guide P P-6 DS785UM1 Copyright 2007 Cirrus Logic
1Introduction 1.1 Introduction The EP93xx processors are highly integrated systems-on-a-chip that pave the way for a multitude of next-generation consumer and industrial electronic products. Designers of digital media servers and jukeboxes, telematic control systems, thin clients, set-top boxes, point-ofsale terminals, industrial controls, biometric security systems, and GPS devices will benefit from the EP93x processors’ integrated architecture and advanced features.
11 1 Introduction EP93xx User’s Guide Table 1-2. EP93xx Features Summary 16-Bit 32-Bit Math CoProcessor External External Processor Bus Bus Raster Analog / LCD 2-D Graphics Accelerator Ethernet MAC IDE Touch PC USB 2.
UART2 with IrDA 1 UART1 with HDLC System Control – 2 PLLs 5-Channel ADC SDRAM MaverickCrunchTM Coprocessor SRAM, FLASH, ROM 2 PWMs Enhanced GPIO, 2-wire, 2 LED ARM920T 12 Channel DMA I 2S 1/10/100 Ethernet MAC JTAG 2 USB 2.0 FS Host I-Cache 16 KB D-Cache 16 KB Memory Management Unit SPI AC’97 RTC with SW Trim Boot ROM High-Speed Bus (AHB) Watchdog Timer Vectored Inerrupts AHB/APB Bridge 4 Timers Peripheral Bus (APB) Figure 1-2.
11 Introduction EP93xx User’s Guide 1 UART2 with IrDA UART1 with HDLC UART3 with HDLC System Control – 2 PLLs 18-bit Raster LCD plus CCITT656 Video SDRAM 8-Wire Touchscreen ADC MaverickCrunchTM Coprocessor 8x8 Matrix Keypad SRAM, FLASH, ROM 2 PWMs ARM920T Enhanced GPIO, 2-wire, 2 LED 12 Channel DMA 1/10/100 Ethernet MAC I-Cache 16 KB D-Cache 16 KB SPI JTAG 3 USB 2.
Features of the EP93xx processors are: • ARM920T Core: • 200 MHz maximum run frequency and 100 MHz maximum high-speed bus frequency for EP9302, 9307, 9312, and 9315 only • 166 MHz maximum run frequency and 66 MHz maximum high-speed bus frequency for EP9301 only • 16 KByte instruction cache and 16 KByte data cache • Memory Management Unit (MMU) with 64-entry Translation-Lookaside-Buffers (TLBs) enable Linux® and Windows® CE® • MaverickCrunch™ Co-processor in EP9302, 9307, 9312, and 9315 only: • Floa
11 Introduction EP93xx User’s Guide - Block Copy - Block Fill 1 • Touch Screen interface - 5-ADC in EP9301 and 9302 only - 8-Wire Touch Screen/ADC in EP9307, 9312, and 9315 only • SPI port • AC ‘97 interface • I2S interface with up to 6 channels • 8x8 Matrix keypad scanner (in EP9307, EP9312, and EP9315 only) • PCMCIA Interface supporting 8-bit or 16-bit PCMCIA (PC Card) devices in EP9315 only • External Memory Options • 16-bit SDRAM interface (up to 4 banks) in EP9301 and 9302 only • 32-
• 16 in EP9312 only • 24 in EP9315 only 1 1.
11 Introduction EP93xx User’s Guide processor simplifies the end-user’s programming task by using predefined co-processor instructions, utilizing standard ARM compiler tools, and by requiring just one debugger session for the entire system. Furthermore, the integrated design provides a single instruction stream and the advantage of zero latency for cached instructions. To emulate this capability, competitors’ solutions add a DSP to the system, which requires separate compiler/linker/debugger tool sets.
1.4.5 Integrated Ethernet MAC Reduces BOM Costs The EP93xx processors integrate a 1/10/100 Mbps Ethernet Media Access Controller (MAC). With a simple connection to MII-based external PHYs (such as the Cirrus Logic CS8952 PHY Transceiver), an EP93xx processor-based system has easy, high-performance, cost-effective Internet capability. 1.4.
11 Introduction EP93xx User’s Guide bits wide, the SMC supports 8-bit, 16-bit, and 32-bit devices, and the SDRAM, SyncROM, and SyncFLASH synchronous memory controller supports 16-bit and 32-bit devices. In the EP9307, EP9312, and EP9315 processors, a separate internal bus to the dynamic memory controller is dedicated to the read-only Raster/Display refresh engine. 1 1.4.
2ARM920T Core and Advanced High-Speed Bus (AHB) 2.1 Introduction This chapter describes the ARM920T Core and the Advanced High-Speed Bus (AHB). 2.2 Overview: ARM920T Core The ARM920T is a Harvard architecture core with separate 16 kbyte instruction and data caches with an 8-word line length. The ARM Core utilizes a five-stage pipeline consisting of fetch, decode, execute, data memory access, and write stages. 2.2.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.2 Block Diagram 2 External Co-Proc Interface Instruction cache Instruction MMU R13 ARM9TDMI Processor core (Integral EmbeddedICE) AMBA Bus Int. CP15 APB Write Buffer R13 JTAG Data cache Data MMU Write Back PA TAG RAM Figure 2-1. ARM920T Block Diagram 2.2.3 Operations The ARM920T core follows a Harvard architecture and consists of an ARM9TDMI core, MMU, instruction and data cache.
A 16 kbyte instruction and a 16 kbyte data cache are included to increase performance for cache-enabled memory regions. The 64-way associative cache also has lock-down capability. A 16-word Write Buffer allows cached instructions to be fetched and decoded while the Write Buffer sends data to external memory. The ARM920T Core supports a number of co-processors, including the MaverickCrunch coprocessor by means of a specific pipeline architecture interface. 2.2.3.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.3.2 Memory Management Unit The MMU provides the translation and access permissions for the address and data ports for the ARM9TDMI core. The MMU is controlled by page tables stored in system memory and accessed using the CP15 register 1. The main features of the MMU are as follows: 2 • Address Translation • Access Permissions and Domains • MMU Cache and Write Buffer Access 2.2.3.2.
2.2.3.2.3 MMU Enable Enabling the MMU allows system memory control, but is also required if the Data Cache and the Write Buffer are to be used. Features are enabled for specific memory regions, as defined in the system page table. MMU enablement is done via CP15 register 1. The procedure is as follows: 1. Program the Translation Table Base (TTB) and domain access control registers 2. Create level 1 and level 2 pages for the system, and enable the Data Cache and the Write Buffer 3.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.3.3.2 Data Cache Enable • A write to bit 2 of CP15 register 1 will enable or disable the Data Cache (D-Cache)/Write Buffer 2 • The D-Cache may only be enabled when the MMU is enabled. All data accesses are subject to MMU and permission checks • If disabled, current contents are ignored. If re-enabled before a reset, contents will be unchanged, but may not be coherent with external memory.
• Latched address and control • A simple Interface to on-chip peripherals such as UARTs and AC’97. C oP roUSB cesso r AR M 9TDM I E x te rn a l M e m o ry In te rfa c e AHB DMA C o n tro lle r AHB/ APB B r i d g e 2 UART SPI APB G P IO AC 97 Figure 2-2. Typical AMBA AHB System 2.2.6 AHB Implementation Details Peripherals or the external memory interface that have high bandwidth and low latency requirements are connected to the CPU using the AHB bus.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 VIC2 VIC1 Ethernet APB ARM920T 18 Bit Raster LCD I/F Touchscreen AHB/APB bridge Boot ROM SDRAM Controller E B I Timers Maverick Crunch 8x8 Key Mtx RTC GPIOs Watchdog Static Memory/ PCMCIA PWM Test Support SPI IDE I2S DMA IrDA USB Host PLL1 AHB PLL2 Clock & State Control UARTs AC97 Figure 2-3. Main Data Paths Before an AMBA-to-AHB transfer can commence, the bus master must be granted access to the bus.
A write data bus is used to move data from the master to a slave, while a read data bus is used to move data from a slave to the master. Every transfer consists of: 2 • An address and control cycle • One or more cycles for the data. In normal operation a master is allowed to complete all the transfers in a particular burst before the arbiter grants another master access to the bus.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.2.8.1 Main AHB Bus Arbiter This Main AHB Bus Arbiter controls bus master arbitration for the AHB bus. The AHB bus has eight master interfaces: 2 • ARM920T • DMA controller • USB hosts (USB1, 2, 3) • Ethernet MAC • LCD/Raster • Raster Hardware Cursor. These interfaces have an order of priority that is linked closely with the power saving modes Halt and Standby.
2.2.8.2 SDRAM Slave Arbiter The SDRAM Slave Arbiter prioritizes between accesses from the AHB bus and the Raster DMA bus. If an access request from the AHB arrives at the same time as an access request from the Raster DMA, the Raster DMA will be given access while the AHB request is queued. 2.2.8.3 EBI Bus Arbiter The EBI Bus Arbiter is used to arbitrate between accesses from the SDRAM controller and the Static Memory controller, where priority is given to accesses from the SDRAM controller. 2.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2.3.2 AHB-to-APB Bridge 2 The AHB-to-APB Bridge is an AHB slave that provides an interface between the high-speed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB. As the APB is not pipelined. Wait states are added during transfers to and from the APB when the AHB is required to wait for the APB.
Note: Due to decoding optimization, the APB peripheral registers are aliased throughout each peripherals register bank. Do not attemp to access an unspecified register within the bank. 22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide 2 2.3.3 APB Slave An APB Slave responds to accesses initiated by bus masters. The slave uses signals from the decoder to determine when it should respond to a bus access.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-5.
• spsr: Saved Program Status Register contains CPSR after occurrence of an exception CP15 has 16 registers that control the core as described in Table 2-6. 2 Table 2-6. CP15 ARM920T Register Description Register Description 0 ID Code: (Read/Only) This register returns a 32-bit device ID code. ID Code data includes the core type, revision, part number etc. Access to this register is via the instruction MRC p15 0, Rd, c0, c0, 0.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-6. CP15 ARM920T Register Description (Continued) 2 Register 11,12,14 Description Reserved 13 FCSE PID Register: (Read/Write) ARM9TDMI core addresses ranging from 0 to 32MB are translated by this register to A + FCSE*32MB and then sent to the MMU. If turned off, straight addresses are sent to the MMU. 15 Test Register Only: Reads or writes will cause unpredictable behavior. 2.3.
Note: The shaded memory areas are dedicated to system registers. Details of these registers are in Table 2-8. 2 2.3.6 Internal Register Map Table 2-8 on page 2-17 shows the memory map for internal registers. Registers are set to their default state by the RSTOn pin input or by the PRSTn pin input. Some state conserving registers are reset only by the PRSTn pin. All registers are read/write unless otherwise specified. 2.3.6.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8. Internal Register Map (Continued) Address 0x8003_006C Register Name Register Description SW Lock CursorColor1 Cursor color overlaid when cursor value is 10 N 0x8003_0070 CursorColor2 Cursor color overlaid when cursor value is 11 N 0x8003_0074 CursorXYLoc Cursor X and Y location Register N 0x8003_0078 CursorDScanLHYLoc Cursor dual scan lower half Y location Register N 0x8003_007C RasterSWLock Software Lock Register.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8. Internal Register Map (Continued) Address Register Name Register Description SW Lock 0x8084_005C IntStsF GPIO Interrupt Status Register. Contains status of Port F interrupts after masking. N 0x8084_0060 RawIntStsF Raw Interrupt Status Register. Contains raw interrupt status of Port F before masking.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8.
22 2 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
Table 2-8.
22 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8.
3MaverickCrunch Co-Processor 3.1 Introduction Note:This chapter applies only to the EP9302, EP9307, EP9312, and EP9315 processors. The MaverickCrunch co-processor accelerates IEEE-754 floating point arithmetic and 32-bit and 64-bit fixed point arithmetic operations. It provides an integer multiply-accumulate (MAC) that is considerably faster than the native MAC implementation in the ARM920T.
33 MaverickCrunch Co-Processor EP93xx User’s Guide • IEEE-754 single precision floating point (24-bit signed significand and 8-bit biased exponent) 3 • IEEE-754 double precision floating point (53-bit signed significand and 11-bit biased exponent) • 32-bit integer • 64-bit integer The co-processor performs the following standard operations on all four supported data formats: • addition • subtraction • multiplication • absolute value • negation • logical left/right shift • comparison In addition, for 32-
• Inexact Note that the division by zero exception is not supported as the MaverickCrunch coprocessor does not provide division or square root. 3 3.1.3 Pipelines and Latency There are two primary pipelines within the MaverickCrunch co-processor. One handles all communication with the ARM920T, while the other, the “data path” pipeline, handles all arithmetic operations (this one actually operates at one half the MaverickCrunch coprocessor clock frequency).
33 MaverickCrunch Co-Processor EP93xx User’s Guide A double precision value requires all 64 bits: Opcode 3 63 62 Sign 52 51 0 Exponent Significand A 32-bit integer is stored in the lower 32 bits of a 64-bit register and sign-extended when written, provided the UI bit in the DSPSC is clear: Opcode 63 32 Sign Extension 31 Sign 30 0 Data Hence, 32-bit integers may be used directly in calculations with 64-bit integers, which are stored as: Opcode 63 62 0 Sign Data 3.1.
With saturation enabled (the default), the maximum representable value is returned on overflow and the minimum representable value is returned on underflow. The maximum and minimum values depends on the operand size and whether the UI bit in the DSPSC is set, as shown in Table 3-1. Table 3-1.
33 MaverickCrunch Co-Processor EP93xx User’s Guide 72 bits wide. If the accumulator saturation mode is disabled (the default), the accumulator bit fields are assigned as below for a 2’s complement integer. 3 Opcode 71 70 0 Sign Data If the saturation mode 1.63 is selected, the bit field assignments are: Opcode 71 64 63 62 0 Sign Extension Sign Data If the saturation mode 1.
condition code field of any subsequent ARM instruction to gate the execution of that instruction based on the result of a Crunch compare operation. Table 3-3 illustrates the legal relationships and, for each one, the values written to the FCC bits and the NZCV flags. The FCC bits and the NZCV flags provide the same information, but in different ways and in different places.
33 MaverickCrunch Co-Processor EP93xx User’s Guide 3.2 Programming Examples The examples below show two algorithms, each implemented using the standard programming languages and the MaverickCrunch instruction set. 3 3.2.1 Example 1 Section 3.2.1.2, Section 3.2.1.3, and Section 3.2.1.4 show three coding samples performing the same operation. Section 3.2.1.1 shows common setup code used by all three samples. Section 3.2.1.2 shows the program implemented in C code. Section 3.2.1.
loop cfmul32 c0, c0, c3 cfsub32 c0, c0, c2 cfcmp32 r15, c0, c1 blt loop cfstr32 c0, [r0, #0x0] ; c0 <= c0 * 5 ; c0 <= c0 - 1 ; c0 < 10 ? ; yes ; no, store result 3 3.2.2 Example 2 The following function performs an FIR filter on the given input stream. The variable “data” points to an array of floating point values to be filtered, “n” is the number of samples for which the filter should be applied, “filter” is the FIR filter to be applied, and “m” is the number of taps in the FIR filter.
33 MaverickCrunch Co-Processor EP93xx User’s Guide cfldrs c3, [r2], #4 cfmuls c1, c2, c3 cfadds c0, c0, c1 subs r12, r12, #4 bne inner_loop sub r0, r3 cfstrs c0, [r0], #4 sub r2, r3 subs r1, r1, #4 bne outer_loop mov pc, lr 3 ; c3 = *filter++; ; c1 = c2 * c3; ; sum += c1; ; j -= 4; ; branch if j != 0 ; data -= m * 4; ; *data++ = sum; ; filter -= m * 4; ; n -= 4; ; branch if n != 0 ; return to caller 3.
DAID: MaverickCrunch Architecture ID. This read-only value is incremented for each revision of the overall MaverickCrunch co-processor architecture. These bits are “000” for this revision. HVID: Hardware Version ID. This read-only value is incremented each time the hardware implementation of the architecture named by DAID[2:0] is changed, typically done in response to bugs. These bits are “000” for this version. ISAT: Integer Saturate Enable.
33 MaverickCrunch Co-Processor EP93xx User’s Guide SAT[1:0]: Accumulator saturation mode select. These bits are set to select the saturation mode or to disable saturation for accumulator operations: 0X = Saturation disabled for accumulator operations 10 = Accumulator saturation enabled, bit formats 1.63 and 1.31 11 = Accumulator saturation enabled, bit format 2.
UFE: Underflow Trap Enable. Enables/disables software trapping for IEEE 754 underflow exceptions: 0 = Disable software trapping for underflow exceptions 1 = Enable software trapping for underflow exceptions OFE: Overflow Trap Enable. Enables/disables software trapping for IEEE 754 overflow exceptions: 0 = Disable software trapping for overflow exceptions 1 = Enable software trapping for overflow exceptions IOE: Invalid Operator Trap Enable.
33 MaverickCrunch Co-Processor EP93xx User’s Guide 3.4 ARM Co-Processor Instruction Format The ARM V4T architecture defines five ARM co-processor instructions: 3 • CDP - Co-processor Data Processing • LDC - Load Co-processor • STC - Store Co-processor • MCR - Move to Co-processor Register from ARM Register • MRC - Move to ARM Register from Co-processor Register The co-processor instruction assembler notation is found in the ARM programming manuals or the Quick Reference Card.
Table 3-5 shows the condition codes, which are bits [31:28] for each instruction format. Table 3-5.
33 MaverickCrunch Co-Processor EP93xx User’s Guide co-processor uses this bit to distinguish between single precision floating point/32-bit integer numbers (N=0) and double precision floating point/64-bit integer numbers (N=1). 3 • W: Specifies whether or not a calculated address is written back to a base register (W=1) or not (W=0). This bit is ignored by the MaverickCrunch co-processor. • offset: An 8-bit word offset used in address calculations.
Table 3-8. MCR Opcode Map op code1 0 cp num [3:0] 0100 0101 0110 3 opcode2[2:0] 000 001 010 011 cfmvdlr cfmv64lr cfmvdhr cfmv64hr cfmvsr cfrshl32 cfrshl64 100 101 110 111 100 101 110 111 cfcmps cfcmp32 cfcmpd cfcmp64 Table 3-9. MRC Opcode Map op code1 0 cp num [3:0] 0100 0101 0110 opcode2[2:0] 000 001 010 cfmvrdl cfmvr64l cfmvrdh cfmvr64h cfmvrs 011 3.
33 MaverickCrunch Co-Processor EP93xx User’s Guide Fields that are ignored by the co-processor are shaded. Dark shading implies that a field is processed by the ARM itself and can have any value, while light shading indicates that the field, though ignored by both the ARM and the co-processor, should have the value shown. 3 Table 3-10.
Table 3-10.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Table 3-10.
Table 3-10.
33 MaverickCrunch Co-Processor EP93xx User’s Guide Bit Definitions: 3 N: Floating point precision - 0 for single, 1 for double. Rn: Base register in ARM CRd: Destination register. Loading Integer Value from Memory 31:28 27:25 24 23 22 21 20 19:16 15:12 11:8 7:0 cond 110 P U N W 1 Rn CRd 0101 8_bit_word_offset Description: Loads a 32- or 64-bit integer from memory into a MaverickCrunch register. Table 3-12.
Mnemonic: Table 3-13. Mnemonic Codes for Storing Floating Point Values to Memory Mnemonic Addressing Mode N CFSTRS CRd, [Rn, ]{!} Immediate pre-indexed 0 CFSTRS CRd, [Rn], Immediate post-indexed 0 CFSTRD CRd, [Rn, ]{!} Immediate pre-indexed 1 CFSTRD CRd, [Rn], Immediate post-indexed 1 3 Bit Definitions: N: Floating point precision - 0 for single, 1 for double. Rn: Base register in ARM CRd: Source register.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide 3.5.2 Move Instructions Move Single Precision Floating Point from ARM to MaverickCrunch 31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 0 0 CRn Rd 0100 010 1 CRm Description: Moves a single precision floating point number from an ARM register into the upper half of a MaverickCrunch register.
Move Lower Half Double Precision Float from MaverickCrunch to ARM 31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 0 1 CRn Rd 0100 000 1 CRm Description: Moves the lower half of a double precision floating point value stored in a MaverickCrunch register into an ARM register.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Move Lower Half 64-bit Integer from ARM to MaverickCrunch 31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 0 0 CRn Rd 0101 000 1 CRm Description: Moves the lower half of a 64-bit integer from an ARM register into the lower half of a MaverickCrunch register and sign extend it.
Move Upper Half 64-bit Integer from MaverickCrunch to ARM 31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 0 1 CRn Rd 0101 001 1 CRm Description: Moves the upper half of a 64-bit integer stored in a MaverickCrunch register into an ARM register. Mnemonic: CFMVR64H Rd, CRn Bit Definitions: Rd: Destination ARM register CRn: Source register 3.5.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Move MaverickCrunch Register to Middle Accumulator 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 10 CRn CRd 0100 011 0 CRm Description: Moves the low 32 bits of a MaverickCrunch register to the middle 32 bits of an accumulator (63:32).
Move High Accumulator to MaverickCrunch Register 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0100 100 0 CRm Description: Moves the highest 8 bits of an accumulator (71:64) to the lowest 8 bits of a MaverickCrunch register (7:0).
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Move 64-bit Integer from Accumulator 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0100 110 0 CRm Description: Saturates and rounds an accumulator value to 64 bits and moves the result to a MaverickCrunch register.
Move from Control/Status Register to MaverickCrunch Register 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0100 111 0 CRm Description: Moves a 64-bit value from the MaverickCrunch Status/Control register, DSPSC, to a MaverickCrunch register. CRn is ignored. Mnemonic: CFMV32SC CRd, CRn Bit Definitions: CRd: Destination register 3.5.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Convert Single Precision Floating Point to Double Precision Floating Point 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 00 CRn CRd 0100 011 0 CRm Description: Converts a single precision floating point value to a double precision floating point value.
Convert 32-bit Integer to Double Precision Floating Point 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 00 CRn CRd 0100 101 0 CRm Description: Converts a 32-bit integer to a double precision floating point value.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Convert Single Precision Floating Point to 32-bit Integer 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0101 100 0 CRm Description: Converts a single precision floating point number to a 32-bit integer.
Bit Definitions: CRd: Destination register CRn: Source register 3 3.5.5 Shift Instructions Shift 32-bit Integer 31:28 27:24 23:22 21 20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 0 0 CRn Rd 0101 010 1 CRm Description: Shifts a 32-bit integer left or right. The shift count is a two’s complement integer stored in an ARM register; the count is positive for left shifts and negative for right shifts.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Shift 32-bit Integer Immediate 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 00 CRn CRd 0101 Shift[6:4] 0 Shift[3:0] Definition: Shift a 32-bit integer by the count specified in the seven bit, two’s complement immediate value. A positive number indicates a left shift and a negative number indicates a right shift.
CFCMPS Rd, CRn, CRm 33 MaverickCrunch Co-Processor EP93xx User’s Guide CRn: First source register 3 CRm: Second source register Rd: Destination ARM register. If Rd = 15, destination is ARM N, C, Z, and V flags.
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Rd: Destination ARM register. If Rd = 15, destination is ARM N, C, Z, and V flags.
Bit Definitions: CRd: Destination register CRn: Source register 3 Single Precision Floating Point Negate 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 11 CRn CRd 0100 010 0 CRm Description: Takes the negative of a single precision floating point number: CRd = -CRn Mnemonic: CFNEGS CRd, CRn Bit Definitions: CRd: Destination register CRn: Source register Double Precision Floating Point Negate 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide Double Precision Floating Point Add 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 11 CRn CRd 0100 101 0 CRm Description: Adds two double precision floating point numbers.
Single Precision Floating Point Multiply 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0100 000 0 CRm Description: Multiplies two single precision floating point numbers: CRd = CRn × CRm Mnemonic: CFMULS CRd, CRn, CRm Bit Definitions: CRd: Destination register CRn: Multiplicand register CRm: Multiplicand register Double Precision Floating Point Multiply 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide 64-bit Integer Absolute Value 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 11 CRn CRd 0101 001 0 CRm Description: Computes the absolute value of a 64-bit integer.
CFADD32 CRd, CRn, CRm 33 MaverickCrunch Co-Processor EP93xx User’s Guide CRd: Destination register 3 CRn: Addend register CRm: Addend register Mnemonic: Bit Definitions: 64-bit Integer Add 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 11 CRn CRd 0101 101 0 CRm Description: Adds two 64-bit integers.
33 MaverickCrunch Co-Processor EP93xx User’s Guide Bit Definitions: 3 CRd: Destination register CRn: Minuend register CRm: Subtrahend register 32-bit Integer Multiply 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0101 000 0 CRm Description: Multiplies two 32-bit integers.
Bit Definitions: CRd: Destination/addend register CRn: Multiplicand register CRm: Multiplicand register 3 32-bit Integer Multiply-Subtract 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0101 011 0 CRm Description: Multiplies two 32-bit integers and subtracts the result from another 32-bit integer: CRd = CRd - (CRn × CRm) Mnemonic: CFMSC32 CRd, CRn, CRm Bit Definitions: CRd: Destination/minuend register CRn: Multiplicand register CRm: Mult
33 3 MaverickCrunch Co-Processor EP93xx User’s Guide 32-bit Integer Multiply-Subtract, Result to Accumulator 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 01 CRn CRd 0110 CRa 0 CRm Description: Multiplies two 32-bit integers, subtracts the product from a third 32-bit integer, and stores the result in an accumulator: CRa = CRd - (CRn × CRm) Mnemonic: CFMSUB32 CRa, CRd, CRn, CRm Bit Definitions: CRa: Destination accumulator CRd: Minuend register CRn: Multi
32-bit Integer Multiply-Subtract from Accumulator 31:28 27:24 23:22 21:20 19:16 15:12 11:8 7:5 4 3:0 cond 1110 00 11 CRn CRd 0110 CRa 0 CRm Description: Multiplies two 32-bit integers, subtracts the product from an accumulator, and stores the result in an accumulator: CRa = CRd - (CRn × CRm) Mnemonic: CFMSUBA32 CRa, CRd, CRn, CRm Bit Definitions: CRa: Destination accumulator CRd: Specifies minuend accumulator CRn: Multiplicand register CRm: Multiplicand register DS785UM1
33 MaverickCrunch Co-Processor EP93xx User’s Guide 3 3-48 DS785UM1 Copyright 2007 Cirrus Logic
4Boot ROM 4.1 Introduction The Boot ROM allows a program or OS to boot from the following devices: • SPI Flash • FLASH, SyncFLASH or SyncROM • UART1 4.1.1 Boot ROM Hardware Operational Overview The Boot ROM is an AHB slave device containing a 16 kbyte mask-programmed ROM. The AHB slave always operates with one wait state, so all data reads from the ROM use 2 HCLK cycles. On system reset, the ARM920T begins executing code at address zero.
44 Boot ROM EP93xx User’s Guide Note that the code retrieved via UART1 and the SPI Serial Flash is not intended to be a complete operating system image. It is intended to be a small (up to 2 kbyte) loader that will, in turn, retrieve a complete operating system image. This small loader can retrieve this complete image through UART1 or the SPI Serial Flash (just as the Boot ROM did) or it can be more sophisticated and retrieve it through the IrDA, USB, or Ethernet interfaces.
8. If it is not a Serial Download, attempt to read from SPI Serial Flash (see Figure 4-1), and then follow Steps A, B, C, and D. A. Check if the first 4 bytes from the Serial Flash are equal to “CRUS” or to “SURC” in ASCII, verifying the HeaderID B. Read the next 2048 (decimal count) bytes into the Internal Boot Buffer C. Turn on Green LED D. Jump to the start of the Internal Boot Buffer 9.
44 Boot ROM EP93xx User’s Guide 4 Start Internal Boot Read Boot State Set Up Clocks Set Up Memory UART Download ? Download Code SPI Boot ? Copy Code Flash Boot ? Boot Flash Boot Download Boot Code Copy SDCS (6 or 7) See 4.2.3 Sync Boot ? Boot Sync SDCS 4.2.4 (0 or 3) See Copy Vectors Flash Green Led Figure 4-1. Flow Chart of Boot ROM Software 4.2 Boot Options Table 4-1 shows configuration settings that are common to all boot modes.
Table 4-1. Boot Configuration Options EECLK EEDAT 0 1 BOOT1 0 BOOT0 0 ASDO CSn[7:6] 1 00 01 10 11 00 01 10 11 External boot using Sync boot mode and SDCSn3. The media type must be either SyncROM or SyncFLASH. The selection of the bus width is determined by latched CSn[7:6] value: 16-bit 16-bit 32-bit 32-bit External boot using Async boot mode and CSn0.
44 Boot ROM EP93xx User’s Guide 4.2.1 UART Boot 4 Make sure that the boot configuration pins (see Table 5-1 on page 5-2) are configured for internal boot mode. EEDAT and BOOT0 should be pulled high and BOOT1 should be pulled low as shown in Table 5-2 on page 5-3. UART 1 is configured at 9600 bps, 8-bits, No Parity, No flow control. The code performs: 1. A single “<“ is output by UART 1 2. The ASCII “CRUS” or “SURC” value in the HeaderID is read 3.
0x3000_1000 0x6000_0000 0x7000_0000 Code execution will start at address FLASH base + 0x0. The ARM Core will be in SVC mode. Note: CSn6 is the recommended chip select for Flash when performing an Internal boot. CSn0 must be connected to Flash when performing an External boot. 4.2.4 SDRAM or SyncFLASH Boot To enable SDRAM or SyncFLASH boot, make sure that the pins are configured for normal boot mode, as shown in Figure 4-2.
44 Boot ROM EP93xx User’s Guide 3. Run the internal boot code and boot from FLASH 4. Set the PLL back to use the external clock 4 5. Set up the SDRAM 6. Load the programs to SDRAM 7.
5System Controller 5.1 Introduction The System Controller (Syscon) provides: • Clock control • Power management • System configuration management These central resources are controlled by a set of software-locked registers, which can be used to prevent accidental accesses. Syscon generates the various bus and peripheral clocks and controls the system startup configuration. 5.1.1 System Startup System startup begins with the assertion of a reset signal. There are five different categories of reset events.
55 System Controller EP93xx User’s Guide certain system variables such as RTC, SDRAM refresh control/global configuration, and the Syscon registers. 5 Note: If PLLs are enabled, user reset does NOT disable or reset the PLLs. They retain their frequency settings. • Three-key reset. When F2, F4, and F7 are pressed, a user reset occurs. • Software reset and watchdog reset. They perform the functions of the user reset, but are under software control.
The normal boot function is described in Chapter 4 on page 4-1. Serial boot is functionally identical to normal boot except that the SBoot bit in the SysCfg register is set. This mode is available for a software configuration option that is readable by the boot code. In either normal boot or serial boot mode, once the processor starts up, it will begin to execute the instruction at logical address 0x0000_0000.
55 5 System Controller EP93xx User’s Guide Note: ASYNC boot mode is the preferred boot mode type for new designs. 5.1.4 Software System Configuration Options There are several system configuration options selectable by the DeviceCfg and SysCfg registers. These registers provide the selection of several pin multiplexing options and also provide software access to the system reset configuration options.
Both PLLs are software programmable (each value is defined in “ClkSet1” on page 5-18 and “ClkSet2” on page 5-20 registers, respectively). The frequency of output clock Fout is determined by: ( PLL1_X1FBD + 1 ) × ( PLL1_X2FBD + 1 )Fout = 14.7456MHz ⋅ --------------------------------------------------------------------------------------------------------PLL1_PS ( PLL1_X2IPD + 1 ) × 2 Here PLL1_X1FBD, PLL1_X2FBD, PLL1_X2IPD and PLL1_PS are the bit fields in the "ClkSet1" register.
55 System Controller EP93xx User’s Guide Syscon 5 32 KHz Oscillator 32 KHz Divide 14.7456 MHz Oscillator PLL1 CFG PLL2 CFG WATCH_CLK Peripheral Clocks UARTxCLK SSPCLK PWMCLK Timer Clocks CPU and Bus Clocks FCLK HCLK PCLK USB and FIR Clocks USBHost48MHz USBHost12MHz FIR_CLK PLL1 Video Clocks PLL2 CPU Audioand Bus Clocks Clocks VCLK SCLK LRCLK MCLK MIR Clock MIR_CLK Key Touch Clock KEY_CLK TOUCH_CLK ADC_CLK FILT_CLK Figure 5-2. Clock Generation System 5.1.5.2.
External Clock PLL1 5 MAX = 500 MHz For 2nd stage dividers: HCLK Div FCLK Div FCLK Divide = 1, 2, 4, 8, 16 HCLK Divide = 1, 2, 4, 5, 6, 8, 16, 32 MAX = 100 MHz MAX = 250 MHz FCLK HCLK PCLK Div MAX = 50 MHz PCLK PCLK Divide = 1, 2, 4, 8 Figure 5-3. Bus Clock Generation There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and PCLK<=50 MHz and FCLK >= HCLK > PCLK.
55 System Controller EP93xx User’s Guide Even though FCLK is the usual CPU clock, HCLK can optionally be used instead. Processor clocking modes are: 5 • Async mode • Sync mode • Fast Bus mode Both Async mode and Sync mode use FCLK. FCLK can be faster than HCLK, which would yield higher performance. Async mode and Sync mode have different clock skew requirements between FCLK and HCLK, and therefor have different throughput penalties due to clock synchronization.
5.1.5.3 Steps for Clock Configuration The boot ROM must contain code that performs the following steps for a 14.7456 MHz crystal. The actual register values should be taken from the register descriptions for the desired clock setup. 5 1. After power up, the reset state of all clock control registers (all bits zero) will ensure that FCLK and HCLK are running at the crystal oscillator frequency of 14.7456 MHz. 2. Configure PLL1 to multiply by the desired value, set HCLK and FCLK rates, and power it up.
55 System Controller EP93xx User’s Guide 5 Table 5-4. Peripherals with PCLK Gating Peripheral Peripheral/PCLK on with Enable or Register Access PCLK on with Register Access Only PCLK Continuous UART1 x - - UART2 x - - UART3 x - - KEYPAD - x - IRDA x - - SEC x - - I2S x - - Watchdog - - x TSC - x - PWM x - - AAC x - - SSP x - - RTC - - x GPIO - x - HCLK to the USB Hosts can be gated off as well to further save power.
5 Power on Reset Read Standby register & SHena = 1 Standby Write to ClkSet1 register Any Enabled Interrupt Run Read Halt register & SHena = 1 Halt Interrupt (if enabled) or return from ClkSet1 Figure 5-4. Power States and Transitions 5.1.6.2.1 Power-on-Reset Run After power-on-reset, the ARM Core is automatically in run mode. 5.1.6.2.
55 5 System Controller EP93xx User’s Guide set. One example of this is when a power-on-reset is applied and this register bit is cleared. This means that this bit will not be set on boot-up and will have to be set to maintain the memory image for when the device re-enters Standby mode. 5.1.6.2.3 RUN HALT mode A transition from Run mode to Halt mode is caused by reading the Halt register location 0x8093_0008 with the SHena bit set to 1.
5.2 Registers This section contains the detailed register descriptions for registers in the Syscon block. Table 5-5 shows the address map for the registers in this block, followed by a detailed listing for each register. Table 5-5. Syscon Register List Address Name SW Locked Type Size Description 0x8093_0000 PwrSts No R 32 Power/state control state 0x8093_0004 PwrCnt No R/W 32 Clock/Debug control status 0x8093_0008 Halt No R 32 Reading this location enters Halt mode.
55 5 System Controller EP93xx User’s Guide Register Descriptions PwrSts 31 30 29 28 27 26 25 24 23 22 21 CHIPMAN 20 19 18 17 16 3 2 1 0 CHIPID 15 14 13 12 11 10 9 8 7 6 WDTFLG RSVD CLDFLG TEST_ RESET RSTFLG SW_ RESET PLL2_ LOCK_REG PLL2_ LOCK PLL1_ LOCK_REG PLL1_ LOCK 5 4 RTCDIV Address: 0x8093_0000 - Read Only Definition: The PwrSts system control register is the Power/State control register. Bit Descriptions: RSVD: Reserved. Unknown During Read.
RSTFLG: Reset flag. This bit is set if the user reset button has been pressed; forcing the RSTOn input low. It is cleared by writing to the STFClr location. On power-on-reset, it is reset to 0b. TEST_RESET: Test reset flag. This bit is set if the test reset has been activated; it is cleared by writing to the STFClr location. On power-on-reset, it is reset to 0b. CLDFLG: Cold start flag. This bit is set if the device has been reset with a power-on-reset; it is cleared by writing to the STFClr location.
55 System Controller EP93xx User’s Guide DMA M2M/P CHx: These bits enable the clocks to the DMA controller channels. Note that a channels-enable bit MUST be asserted before any register within the DMA controller can be read or written. At least one ARM instruction cycle must occur between writing to this register to enable the DMA Controller channel and actually accessing it. The number of cycles will depend on the setting of HCLK and PCLK division in the "ClkSet1" or "ClkSet2" register.
Standby and Halt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD Address: Standby - 0x8093_000C - Read Only Halt - 0x8093_0008 - Read Only Definition: The Standby and Halt registers allow entry into the power saving modes. A read to the Halt location will initiate a request for the system to enter Halt mode, if the SHena bit is set in the DeviceCfg register in Syscon.
55 5 System Controller EP93xx User’s Guide STFClr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD Address: 0x8093_001C - Write Definition: Writing to the STFClr location will clear the CLDFLG, WDTFLG and RSTFLG in the register, “PwrSts” on page 5-14. Any data written to the register triggers the clearing. Bit Descriptions: RSVD: There are no readable bits in this register.
PLL1_X2FBD2: These 6 register bits set the first feedback divider bits for PLL1. On power-on-reset the value is set to 000111b (7 decimal). Note: The value in the register is the actual coefficient minus one. PLL1_X1FBD1: These 5 register bits set the second feedback divider bits for PLL1. On power-on-reset the value is set to 10011b (19 decimal). Note: The value in the register is the actual coefficient minus one. PLL1_PS: These two bits determine the final divide on the VCO clock signal in PLL1.
55 System Controller EP93xx User’s Guide nBYP1: This bit selects the clock source for the processor clock dividers. With this bit clear, the system wakes up and boots with the PLL bypassed and uses an external clock source. With nBYP1 set, the system runs with the PLL generated clock. The default for this bit is to boot/run from external clock source. SMCROM: If set, this bit will gate off the HCLK to the Static Memory Controller when in Halt mode and therefore save power.
PLL2_X2FBD2: These 6 register bits set the first feedback divider bits for PLL2. On power-on-reset the value is set to 11000b (24 decimal). Note: The value in the register is the actual coefficient minus one. PLL2_X1FBD1: These 5 register bits set the second feedback divider bits for PLL2. On power-on-reset the value is set to 11000b (24 decimal). Note: The value in the register is the actual coefficient minus one.
55 5 System Controller EP93xx User’s Guide ScratchReg0, ScratchReg1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Value 15 14 13 12 11 10 9 8 Value Address: ScratchReg0 - 0x8093_0040, Read/Write ScratchReg1 - 0x8093_0044, Read/Write Default: 0x0000_0000 Definition: Each of these locations provide a 32-bit read/write scratch register, that can be used as a general purpose storage. These registers are reset to zero only on a power-on-reset.
BusMstrArb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 RSVD 15 14 13 12 11 RSVD 10 RSVD 9 8 7 6 5 4 3 2 MAC ENFIQ MAC ENIRQ USH ENFIQ USH ENIRQ DMA_ ENFIQ DMA_ ENIRQ PRI CORE RSVD PRI_ORD Address: 0x8093_0054 - Read/Write Definition: The Bus Master arbitration register (BusMstrArb) is used to configure the AHB master priority order. Bit Descriptions: RSVD: Reserved. Unknown During Read. PRI_ORD: Used to set the priority of the AHB arbiter.
55 System Controller EP93xx User’s Guide DMA_ENFIQ: When set the arbiter will degrant DMA from the AHB bus and will ignore subsequent requests from DMA if an FIQ is active. When FIQ is cleared the DMA request is allowed again. There is no impact on other masters. Reset to 0. USH_ENIRQ: When set the arbiter will degrant USB host from the AHB bus and will ignore subsequent requests from the USB Host if an IRQ is active. When IRQ is cleared, the USB Host request is allowed again.
DeviceCfg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SWRST D1onG D0onG IonU2 GonK TonG MonG U3EN CPENA A2onG A1onG U2EN EXVC U1EN TIN RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HC3IN HC3EN HC1IN HC1EN HonIDE GonIDE PonG EonIDE I2Son SSP I2Son AC97 0 RASOn P3 RAS ADCPD KEYS SHena Address: 0x8093_0080 - Read/Write, Software locked Default: 0x0000_0000 Definition: Device Configuration Register.
55 System Controller EP93xx User’s Guide I2SonAC97: 5 Audio - I2S on AC97 pins. The I2S block uses the AC97 pins. See Audio Interface pin assignments in Table 5-7. Note: The I2S should be enabled on only one set of pins. Therefore I2SonAc97 and I2SonSSP are mutually exclusive. Setting both I2SonAc97 and I2SonSSP will cause unexpected behavior. I2SonSSP: Audio - I2S on SSP pins. The I2S block uses the SSP pins. MCLK is not available in this pin option. See Audio Interface pin assignments in Table 5-7.
0 - GPIO Port H used for IDE 1 - GPIO Port H used for GPIO HC3IN: HDLC3 clock in. This bit has no effect unless HC3EN is 1. 1 = pin EGPIO[3] is an input and drives an external HDLC clock to UART3. 0 = pin EGPIO[3] is an output driven by UART3. HC3EN: HDLC3 clock enable. 1 = pin EGPIO[3] is used to for an HDLC clock with UART3. 0 = pin EGPIO[3] is not used. HC1IN: HDLC1 clock in. This bit has no effect unless HC3EN is 0 and HC1EN is 1.
55 System Controller EP93xx User’s Guide A1onG: I2S Audio Port 1 on GPIO. 1 - I 2 S Port 1 pins are mapped to EGPIO. SDI1 is on EGPIO[5], SDO1 is on EGPIO[4]. 0 - EGPIO[5:4] are not used. A2onG: I2S Audio Port 2 on GPIO. 1 - I 2 S Port 2 pins are mapped to EGPIO. SDI2 is on EGPIO[13], SDO2 is on EGPIO[6]. 0 - EGPIO[13] and EGPIO[6] are not used. CPENA: Co-processor Enable. 1 - MaverickCrunch co-processor is enabled.
SWRST: Software reset. A one to zero transition of this bit initiates a software reset. VidClkDiv 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 VENA ESEL PSEL 12 11 10 RSVD 9 8 PDIV RSVD VDIV Address: 0x8093_0084 - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures video clock for the raster engine. Selects input to VCLK dividers from either PLL1 or PLL2, and defines a programmable divide value.
55 5 System Controller EP93xx User’s Guide MIRClkDiv 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 MENA ESEL PSEL 12 11 10 RSVD 9 8 PDIV RSVD MDIV Address: 0x8093_0088 - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures MIR clock for the MIR IrDA. Selects input to MIR clock dividers from either PLL1 or PLL2, and defines a programmable divide value. Bit Descriptions: RSVD: Reserved. Unknown During Read.
I2SClkDiv 31 30 29 SENA SLAVE ORIDE 15 14 13 MENA ESEL PSEL 28 27 26 25 24 23 22 21 RSVD 12 11 10 RSVD 9 8 PDIV 7 6 5 20 19 DROP SPOL 4 3 RSVD 18 17 LRDIV 2 16 SDIV 1 0 MDIV Address: 0x8093_008C - Read/Write, Software locked Default: 0x0000_0000 Definition: Configures the I2S block audio clocks MCLK, SCLK, and LRCLK. Bit Descriptions: RSVD: Reserved. Unknown During Read. SENA: Enable audio clock generation. SLAVE: I2S slave.
55 System Controller EP93xx User’s Guide 5 SDIV: SCLK divide select. 1 - SCLK = MCLK / 4, 0 - SCLK = MCLK / 2. MENA: Enable master clock generation. ESEL: External clock source select. 0 - Use the external XTALI clock input as the clock source. 1 - Use one of the internal PLLs selected by PSEL as the clock source. PSEL: PLL source select. 1 - Select PLL2 as the clock source. 0 - Select PLL1 as the clock source. PDIV: Pre-divider value. Generates divide by 2, 2.5, or 3 from the clock source.
ADIV: ADC clock divider value. 0 - ADC Clock is divide-by-16 from the external oscillator. 1 - ADC Clock is divide-by-4 from the external oscillator. KEN: Key matrix clock enable. This clock is divided from the slow clock source. KDIV: Key matrix clock divider value. 0 - Key Matrix Clock is divide-by-16 from the external oscillator. 1 - Key Matrix Clock is divide-by-4 from the external oscillator.
55 5 System Controller EP93xx User’s Guide SysCfg 31 30 29 28 27 26 25 24 23 22 REV 15 14 21 20 19 18 17 16 RSVD 13 12 11 10 9 RSVD 8 7 6 5 4 3 2 1 0 SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1 Address: 0x8093_009C - Read/Write, Software locked Default: 0x0000_0000 Definition: System Configuration Register. Provides various system configuration options. Bit Descriptions: RSVD: Reserved. Unknown During Read.
LCSn1, LCSn2: Define Watchdog startup action: 00 - Watchdog disabled, Reset duration disabled 01 - Watchdog disabled, Reset duration active 10 - Watchdog active, Reset duration disabled 11 - Watchdog active, Reset duration active 5 SysSWLock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD LOCK Address: 0x8093_00C0 - Read/Write Default: 0x0000_0000 Definition: Syscon Software Lock Register.
55 System Controller EP93xx User’s Guide 5 5-36 DS785UM1 Copyright 2007 Cirrus Logic
6Vectored Interrupt Controller 6.1 Introduction The EP93xx processors contain two cascaded Vectored Interrupt Controllers (VIC). A Vectored Interrupt has improved latency compared with a simple interrupt controller, since it provides direct information about where the interrupt’s service routine is located and eliminates levels of software arbitration. Each individual Vectored Interrupt Controller can handle up to 32 interrupts, but there are more than 32 interrupts in this design.
66 Vectored Interrupt Controller EP93xx User’s Guide 6 2 Vector Addr from VIC1 VICINTSOURCE[63:32] Vector Address and Priority Logic FIQ from VIC12 IRQ from VIC12 2 VIC1 ARM920T VIC Daisy Chain IRQ VICINTSOURCE[31:0] Vector Address and Priority Logic FIQ VIC01 Figure 6-1. Vectored Interrupt Controller Block Diagram 6.1.
Any 16 of the 32 interrupts (per VIC) can be designated as ‘vectored’ by programming the Vector address registers, ‘VICxVectAddr0’ on page 6-15 and the Vector Control registers, ‘VICxVectCntl0,’ on page 6-17. An interrupt is designated as either IRQ or FIQ by programming the VICxIntSelect register. The IRQ and FIQ request logic has an asynchronous path. This allows interrupts to be asserted when the clock is disabled.
66 Vectored Interrupt Controller EP93xx User’s Guide Table 6-1.
TC1UI Timer Counter 1 Under Flow Interrupt. When Timer Counter 1 has underflowed (reached zero), this interrupt becomes active on the next falling edge of the timer’s clock. The interrupt is cleared by writing any value to the “Timer1Clear,” register. See Chapter 18, "Timers". TC2UI Timer Counter 2 Under Flow Interrupt. When Timer Counter 2 has underflowed (reached zero), this interrupt becomes active on the next falling edge of the timer’s clock.
66 Vectored Interrupt Controller EP93xx User’s Guide UART1TXINTR1 6 UART 1 Transmit Interrupt. See Chapter 14, "UART1 With HDLC and Modem Control Signals". UART1RXINTR2 UART 2 Receive Interrupt. See Chapter 15, "UART2"”. UART1TXINTR2 UART 2 Transmit Interrupt. See Chapter 15, "UART2"”. UART1RXINTR3 UART 3 Receive Interrupt. See Chapter 16, "UART3 With HDLC Encoder". UART1TXINTR3 UART 3 Transmit Interrupt. See Chapter 16, "UART3 With HDLC Encoder". INT_KEY Key Matrix Interrupt.
CLK1HZ 1 Hz clock interrupt. See Chapter 20, "Real Time Clock With Software Trim". V_SYNC Vertical or Composite Sync/Frame Pulse Interrupt. See Chapter 7, "Raster Engine With Analog/LCD Integrated Timing and Interface". 6 INT_VIDEO_FIFO Video FIFO Interrupt. See Chapter 7, "Raster Engine With Analog/LCD Integrated Timing and Interface" INT_SSP1RX SSP Receive Interrupt. See Chapter 23 "Synchronous Serial Port". INT_SSP1TX SSP Transmit Interrupt. See Chapter 23 "Synchronous Serial Port".
66 Vectored Interrupt Controller EP93xx User’s Guide 6 INT_DSP ARM Core interrupt. GPIOINTR Combined Interrupt from Any Bit in Ports A or B. See Chapter 28, "GPIO Interface" I2SINTR Combined Interrupt of All Sources from the I2S Controller. See Chapter 21, "I2S Controller" 6.2 Registers The 2 VIC blocks have an identical register definition.
Table 6-2.
66 Vectored Interrupt Controller EP93xx User’s Guide Definition: IRQ Status Register. The VICxIRQStatus register provides the status of interrupts after IRQ masking. Interrupts 0 - 31 are in VIC1IRQStatus. Interrupts 32 - 63 are in VIC2IRQStatus. 6 Bit Descriptions: IRQStatus: Shows the status of the interrupts after masking by the VICxIntEnable and VICxIntSelect registers. A “1” indicates that the interrupt is active, and generates an interrupt to the ARM Core.
Definition: The VICxRawIntr register provides the status of the source interrupts (and software interrupts) to the interrupt controller. Bit Descriptions: RawIntr: Shows the status of the interrupts before masking by the enable registers. A “1” indicates that the corresponding interrupt request is active before masking.
66 Vectored Interrupt Controller EP93xx User’s Guide Definition: Interrupt Enable Register. The VICxIntEnable register enables the interrupt requests by unmasking the interrupt sources. On reset, all interrupts are disabled (masked). 6 Bit Descriptions: IntEnable: Enables the interrupt request lines: 1 - Interrupt enabled. Allows interrupt request to ARM Core. 0 - Interrupt disabled.
Default: Don’t Care Definition: Software Interrupt Register. The VICxSoftInt register is used to generate software interrupts. Bit Descriptions: SoftInt: Writing a bit to “1” generates a software interrupt for the corresponding source interrupt before interrupt masking. Writing a bit to “0” has no effect.
66 Vectored Interrupt Controller EP93xx User’s Guide Definition: Protection Enable Register. The VICxProtection register enables or disables protected register access. If the bus master cannot generate accurate protection information, leave this register in its reset state to allow User mode access. 6 Bit Descriptions: RSVD: Reserved. Unknown During Read. Protection: Enables or disables protected register access.
If you are not using the priority level in the VIC, write the VICxVectAddr register with any value (in order to disable the interrupt priority) at the beginning of your program. It is not always clear when the ARM debuggers read the VICxVectAddr register, so it is recommended that if you are using a debugger, do not read the VIC registers via a memory window. If you must read the VIC registers, read only the VIC registers that are needed.
66 6 Vectored Interrupt Controller EP93xx User’s Guide VICxVectAddr7, VICxVectAddr8, VICxVectAdd9, VICxVectAddr10, VICxVectAddr11, VICxVectAdd12, VICxVectAddr13, VICxVectAddr14, VICxVectAddr15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 VectorAddr 15 14 13 12 11 10 9 8 7 VectorAddr Address: VIC1VectAddr0: 0x800B_0100 - Read/Write VIC1VectAddr1: 0x800B_0104 - Read/Write VIC1VectAddr2: 0x800B_0108 - Read/Write VIC1VectAddr3: 0x800B_010C - Read/Write VIC1V
VIC2VectAddr6: 0x800C_0118 - Read/Write VIC2VectAddr7: 0x800C_011C - Read/Write VIC2VectAddr8: 0x800C_0120 - Read/Write VIC2VectAddr9: 0x800C_0124 - Read/Write VIC2VectAddr10: 0x800C_0128 - Read/Write VIC2VectAddr11: 0x800C_012C - Read/Write VIC2VectAddr12: 0x800C_0130 - Read/Write VIC2VectAddr13: 0x800C_0134 - Read/Write VIC2VectAddr14: 0x800C_0138 - Read/Write VIC2VectAddr15: 0x800C_013C - Read/Write 6 Definition: Vector Address Registers.
66 6 Vectored Interrupt Controller EP93xx User’s Guide VICxVectCntl15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD E IntSource Address: VIC1VectCntl0: 0x800B_0200 - Read/Write VIC1VectCntl1: 0x800B_0204 - Read/Write VIC1VectCntl2: 0x800B_0208 - Read/Write VIC1VectCntl3: 0x800B_020C - Read/Write VIC1VectCntl4: 0x800B_0210 - Read/Write VIC1VectCntl5: 0x800B_0214 - Read/Write VIC1VectCntl6: 0x800B_0218 - Read/Write VIC1Ve
Note: Vectored interrupts are only generated if the interrupt is enabled. The specific interrupt is enabled in the VICxIntEnable register, and the interrupt is set to generate an IRQ interrupt in the VICxIntSelect register. This prevents multiple interrupts being generated from a single request if the controller is incorrectly programmed. 6 Bit Descriptions: RSVD: Reserved. Unknown During Read. E: Enables vector interrupt. This bit is cleared to ‘0’ on reset.
66 Vectored Interrupt Controller EP93xx User’s Guide 6 6-20 DS785UM1 Copyright 2007 Cirrus Logic
Chapter 7 7Raster Engine With Analog/LCD Integrated Timing and Interface 7.1 Introduction Note: This chapter applies only to the EP9307, EP9312, and EP9315 processors. For additional information regarding the use of t he EP93XX Raster Engine, see the application note, AN269, “Using the EP93xx’s Raster Engine” at: http://www.cirrus.com/en/pubs/appNote/AN269REV1.pdf. The Raster engine is capable of providing data and timing signals for a variety of displays.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide The Raster engine also supports several hardware blinking modes, and 8-bit addressed lookup tables for grayscale or expanding color depth. The Raster also includes a video stream signature generator for built in self-testing. 7 Examples for some of the possible output modes are shown in Table 7-1. Table 7-1.
Table 7-1. Raster Engine Video Mode Output Examples Frame Buffer Storage Format Display Data Format Pixels Per Shift Clock Pixel Shift Clock Freq. (MHz) Vertical Frame Rate (Hz) Display Type Horizontal Vertical x Resolution Resolution Video Clock Freq.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide to one pixel combination blinking. For 16 bpp and 24 bpp modes, the LUT blink circuitry is usually bypassed and the blink functions are logic transformations of the pixel data. In addition to logical AND/OR/XOR LUT address translations, the circuitry will support logical blink to background, blink dim, blink bright, and blink to reverse. 7 7.3.
most significant location on a per byte basis. Table 7-2 demonstrates pixel packing within words in a byte oriented Frame Buffer organization. 7 Table 7-2.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Table 7-2.
brightness control. The Bright output signal can also be used for direct pulse width modulated CCFL brightness control that can be synchronized to the display frame rate. 7.3.7 Hardware Cursor The Raster Engine provides hardware cursor support. The cursor size is programmable up to 64 pixels wide by 64 pixels in height. The cursor is stored anywhere in memory as a 2 bpp image. The 2 bpp image pixel information implies transparent, inverted, cursor color 1, or cursor color 2.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 24 7 FIFO YCrCb Encoder P[17:0] 64 Pixel MUX DAT(31:0) Video Image Line Output Scanner And Transfer Interface ADR(31:0) IN ADR CTR 24 Blink Logic 8 256x24 SRAM Look Up Table 3 Gray Scale Gen 24 Two 32x32 Dual Port RAMs 24 Color MUX PELEN Pixel Shifting Logic CCIREN 24 S/PCLK OUT ADR CTR PCLKEN 24 N_WR Video Stream Signature Analyzer FULL HFULL N_CLR To DAC N_RD Control Logic HADR(31:0) Cursor
register, “VidScrnPage” on page 7-46. For a dual scan display, information from the upper left corner of the lower half of the display begins at the word address stored in the “VidScrnHPage” register. The “VidScrnPage” and “VidScrnHPage” registers are used to preload address counters at the beginning of the video frame. The VILOSATI continues to service the video FIFO until it has transferred an entire screen image from memory.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide words on both the upper and lower half of the bus. The FIFO has an underflow interrupt indicator that can be used to determine if the system is providing adequate bandwidth and low enough latency to support the selected display pixel depth, resolution, and refresh rate. 7 7.4.
this mode will cause an object to appear and disappear. A drawback to this mode is that it may cause problems with correctly viewing overlapping objects. Blink Brighter and Blink Dimmer modes shift the pixel data values by one bit position. For Blink Brighter, the LSB is dropped, the MSBs are all shifted one bit lower, and the MSB is set to a “1”. For Blink Dimmer, the LSB is dropped, the MSBs are all shifted one bit lower, and the MSB is set to a “0“.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide data into the unused LSBs of the bus to support the full color intensity range. This part of the multiplexing circuitry actually occurs before the blink logic stage. Once selected and conditioned, output data is sent to the pixel shift logic and the YCrCb logic. The data is further conditioned with blanking in another pipeline operation before being sent to a color DAC. 7 7.4.
Shift Color Mode Mode 0x0 0x4 0x8 0x0 0x5 0x0 0x6 0x1 0x0 0x4 0x8 0x1 0x5 0x1 0x6 0x2 0x0 0x8 0x3 0x0 0x8 0x4 0x0 0x8 0x5 0x0 0x8 P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) single pixel per clock up R(1) R(0) to 24 bits wide single 16-bit 565 pixel per R(3) R(2) clock single 16-bit 555 pixel per R(3) R(2) clock single 24-bit pixel mapped X X to 18 bits each clk single 16-bit 565 pixel mapped to X X 18 bits each clk single 16-
DS785UM1 Table 7-3.
7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays The hardware raster engine has three built in matrix programmable grayscale generators. One generator is located on each of the red, green, and blue internal channels. These generators can be enabled to expand color depth or turn monochrome into grayscale through both spatial and temporal dithering.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Assuming that pixel input value 0 is off, setting raster engine base + grayscale LUTx offset + 0x00, 0x20, 0x40, and 0x60 to all ‘0’s ensures that a 0 pixel never turns on. Assuming that pixel 7 is full on, setting raster engine base + grayscale LUTx offset + 0x1C, 0x3C, 0x5C, and 0x7C to all ‘1’s ensures that the value is always on. Table 7-6 shows the format for programming. 7 7.4.8.
7.4.8.7 Grayscale Look-Up Table (GrySclLUT) 7 Table 7-4.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Where FRAME[1:0] = FRAME_CNT3 or FRAME_CNT4 as defined by FRAME at address Pixel_In, 7 VCNT[1:0] = VERT_CNT3 or VERT_CNT4 as defined by VERT at address Pixel_In, and HCNT[1:0] = HORZ_CNT3 or HORZ_CNT4 as defined by HORZ at address Pixel_In. This is the GrySclLUT table in an easily readable form.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Table 7-5.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide The values in between full on and full off are more difficult to determine and depend on the display characteristics such as persistence, turn on time, and refresh rate. To achieve difference in shades of gray, it is typical to have more values below the half luminance average due to the higher sensitivity to luminance variations by the human eye at lower levels.
Frame 0 H O R Z 1 0 1 0 0 1 0 1 E 1 0 1 0 0 1 0 1 R 1 0 1 0 0 1 0 1 T 1 0 1 0 0 1 0 1 Frame 2 7 Frame 1 V Frame 3 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 Figure 7-4. Sample Matrix Causing Flickering To minimize these type of spatial interference patterns, it is better to mix up the pattern sequence similar to that shown in Figure 7-5.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Assuming the 3 bit input pattern that represents this 50% duty cycle grayscale is 0x3 (or 011b), the values in Table 7-7 should be used to program this pattern into the grayscale lookup-table. 7 Table 7-7.
Please note that as the frame number progresses, the bit pattern in each row moves to the right one pixel. This type of pattern shown in an area may cause diagonal lines to appear as though they are moving to the right. As previously stated, any image distortion greatly depends on the application. However, the pattern shown in Figure 7-7 will have less of a tendency to demonstrate a walking distortion.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 7 Frame 0 H O R Z Frame 1 V 1 0 0 0 0 1 0 0 E 0 0 1 1 0 1 0 0 R 0 1 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 T Frame 2 Figure 7-8. Three and Four Count Axis Assuming that the 3-bit input pattern that represents this 33% duty cycle grayscale is 0x2 or 010b, the values in Table 7-9 are used to program this pattern into the grayscale look-uptable.
“Start” is the beginning word location of the part of the cursor image to be displayed first. The image is 2-bits per pixel, and is stored linearly. The amount of storage space is dependent on the width and height of the cursor. The two bits per pixel stored define screen image (transparent), invert screen image, display color1, and display color2.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide The X location value controls the starting horizontal X location of the cursor image. The value is compared to the horizontal pixel counter and should be set by software to be between the active start and active stop horizontal pixel values. The cursor hardware will clip the cursor at the right edge of the screen.
CLINS Six bits select the height of the cursor image. The height is measured in lines and should be set to a value of one less then the desired number of lines. CWID Two bits select the cursor width: 00 0 10 11 Width is 1 word or 16 pixels 1Width is 2 words or 32 pixels Width is 3 words or 48 pixels Width is 4 words or 64 pixels DLNS Six bits are used in DUAL SCAN mode, where DUAL SCAN mode is selected by writing DSCAN = ‘1’ to the “PixelMode” register. 7.4.9.1.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 7.4.10 Video Timing 7 The video timing circuitry consists of a horizontal down counter and a vertical down counter. Signal timing for a specific video format is generated by programmable values that are compared to the count values. An AC signal is generated to support either bias voltage switching for LCDs or a field indicator for interlaced video.
7 VLINESTOTAL Vertical down counter 0h 1h VLINESTOTAL VLINESTOTAL -1 0h VLINESTOTAL VSYNCSTART VSYNCSTOP VCLKSTOP VCLKSTART VACTIVESTRT VACTIVESTOP Vertical Back Porch VSYNCn Vertical Front Porch Vertical Active Video Vertical Sync Interval VACTIVE VBLANKn VBLANKSTRT VBLANKSTOP SPCLK DURING Vertical LINECARRY (CLKS) Horizontal down counter HCLKSTOTAL HCLKSTOTAL 0h 1h 0h HCLKSTOTAL -1 HSYNCSTART HSYNCSTOP HCLKSTOP HCLKSTART HACTIVESTRT HACTIVESTOP HSYNCn Horizontal Active Video Horizontal
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Vertical down counter 7 VLINESTOTAL 0h 1h VLINESTOTAL 0h VLINESTOTAL VSYNCSTART VSYNCSTOP VSYNCn FIELD1 FIELD0 VCLKSTRT VCLKSTOP VACTIVESTOP VACTIVESTRT VLINESTOTAL/2 CURSORDSCANHYLOC HSIGSTOP HSIGSTRT VSIGSTOP VSIGSTRT VACTIVE VBLANKn VBLANKSTOP VBLANKSTRT SPCLK DURING Vertical LINECARRY (CLKS) Horizontal down counter HCLKSTOTAL HCLKSTOTAL 0h 1h 0h HCLKSTOTAL -1 HSYNCSTART HSYNCSTOP HCLKSTOP HCLKSTART H
7.4.10.1 Setting the Video Memory Parameters The Raster Engine uses SDRAM for video frame buffers. The SDRAM locations for the video frame buffers are defined by four registers: “VidScrnPage” , “ScrnLines” , “LineLength” , and “VLineStep” . 7.4.10.1.1 Setting up the VidScrnPage Register The VidScrnPage register provides the starting address for the video memory relative to the beginning of SDRAM memory space.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide VLineStep = 640 x 4bpp/32 7.4.10.2 PixelMode Pixel data is transferred from the FIFO to the Video Pixel Mux two 32-bit words at a time (total of 64 bits). Bits[2:0] of the “PixelMode” register specify the pixel depth as shown in Table 711. The Video Pixel MUX uses the “PixelMode” register to determine how many pixels are contained in the 64 bits of data.
7.4.11.2.1 PattrnMask Register This register defines which bits in a pixel are blink bits. To enable an individual bit for comparison requires setting that corresponding bit to “1”. To disable an individual bit for comparison set the bit position to “0”. 7 For example, in 8bpp mode, the PattrnMask is defined as 0x0000_0080. This means that the MSB of a pixel is used to assist is defined as a blink bit. 7.4.11.2.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide If the LUT is enabled, the pixel data is passed to the LUT. The new pixel data value will be used to index into the LUT. The value at that index location will be passed on to the Color Mux. 7 Non LUT Blink: If the LUT is not enabled, the modified pixel data is moved directly into the Color Mux. This new pixel value is used by the Color Mux as the 'new' value for the blinking pixel.
1. The MSB is dropped 2. The remaining bits are shifted left by one 7 3.The LSB is set to ‘1’ 1110 - Dim 888 Blinking: The 24 bits of data is made up of three 8-bit values that represent the RGB colors. Each of the 8 bit values is treated as a single value, and the blinking rules defined for the Dim Single Blinking mode are applied. 1111 - Bright 888 Blinking: The 24 bits of data is made up of three 8-bit values that represent the RGB colors.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 7.5 Registers 7 Table 7-12.
Table 7-12. Raster Engine Register List (Continued) Address Name SW locked Type Size Description 0x8003_0060 CursorAdrStart No Read/Write 32 bits Word location of the top left corner of cursor to be displayed. 0x8003_0064 CursorAdrReset No Read/Write 32 bits Location of first word of cursor to be scanned after last line. 0x8003_0068 CursorSize No Read/Write 16 bits Cursor height, width, and step size register.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Vertical Frame Timing Registers VLinesTotal 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD TOTAL Address: 0x8003_0000 Default: 0x0000_0000 Definition: Total horizontal lines that compose a vertical frame Bit Descriptions: RSVD: Reserved - Unknown during read TOTAL: VLines Total - Read/Write The VLines Total value written to this fiel
When the Vertical counter counts down to the written STOP value, the VSYNC signal on the V_CSYNC pin will go inactive if CSYNC = ‘0’ and SYNCEN = ‘1’ in the VideoAttribs register. Please refer to the video signalling timing diagrams shown in Figure 7-9 and Figure 7-10. STRT: Start - Read/Write When the Vertical counter counts down to the written STRT value, the VSYNC signal on the V_CSYNC pin will go active if CSYNC = ‘0’ and SYNCEN = ‘1’ in the VideoAttribs register.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide VBlankStrtStop 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 13 21 20 19 18 17 16 4 3 2 1 0 STOP 12 11 10 9 8 7 6 RSVD 5 STRT Address: 0x8003_0228 Default: 0x0000_0000 Definition: Vertical BLANK signal Start/Stop register Bit Descriptions: RSVD: Reserved - Unknown during read STOP: Stop - Read/Write The STOP value is the value of the Vertical down counter at which the VBLANKn signal bec
VClkStrtStop 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 13 21 20 19 18 17 16 4 3 2 1 0 STOP 12 11 10 9 8 7 6 RSVD 5 STRT Address: 0x8003_000C Default: 0x0000_0000 Definition: Vertical Clock Start/Stop register Bit Descriptions: RSVD: Reserved - Unknown during read STOP: Stop - Read/Write The STOP timing register contains the value of the Vertical down counter at which the VCLKEN signal goes inactive (stops).
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Horizontal Frame Timing Registers HClkTotal 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD TOTAL Address: 0x8003_0010 Default: 0x0000_0000 Definition: Total pixel clocks that compose a horizontal line Bit Descriptions: RSVD: Reserved - Unknown during read TOTAL: Total - Read/Write The HClk Total timing register contains the total num
The STOP value is the horizontal down counter value at which the HSYNCn signal becomes inactive (stops). When the Horizontal counter counts down to the STOP value, the HSYNCn signal goes inactive. Please refer to video signalling timing diagrams in Figure 7-9 and Figure 7-10. STRT:Start - Read/Write The STRT value is the horizontal down counter value at which the HSYNCn signal becomes active (starts). When the Horizontal counter counts down to the STRT value, the HSYNCn signal goes active (starts).
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide STRT: Start - Read/Write The STRT value is the value of the Horizontal down counter at which the HACTIVE signal becomes active (starts). This indicates the start of the active video portion for the Horizontal line. Please refer to video signalling timing diagrams in Figure 7-9 and Figure 7-10. HACTIVE is an internal block signal. The active video interval is controlled by the logical OR of VACTIVE and HACTIVE.
HClkStrtStop 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 13 21 20 19 18 17 16 4 3 2 1 0 STOP 12 11 10 9 8 7 6 RSVD 5 STRT Address: 0x8003_001C Default: 0x0000_0000 Definition: Horizontal Clock Active Start/Stop register Note: When horizontal clock gating is required, set the STRT and STOP fields in the HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a programming requirement that is easily overlooked.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Frame Buffer Memory Configuration Registers VidScrnPage 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 21 20 19 18 17 16 5 4 3 2 1 0 PAGE 13 12 11 10 9 8 7 6 PAGE NA Address: 0x8003_0028 Default: 0x0000_0000 Definition: Video Screen Page Register Bit Descriptions: RSVD: Reserved - Unknown during read PAGE: Video Screen Page Starting SDRAM Address - Read/Write Corresponds to the word add
PAGE: Video Screen Half-page Starting SDRAM Address Read/Write If DSCAN = ‘1’ in the PixelMode register, the Video Screen Half-page Starting SDRAM Address value written to this field corresponds to the upper left corner of the bottom half of the video screen. NA: Not Assigned. Will return written value during a read.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide LEN: Length - Read/Write The Length value written to this field specifies, in 32-bit words, the length of video lines that are scanned to the display. Please see “Setting up the LineLength Register” on page 7-31 and “Memory Setup Example” on page 7-31. 7 The remainder of the last word in a video line may not be used as long as the blanking time is greater than the remaining number of pixels.
LineCarry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD LCARY Address: 0x8003_003C Default: 0x0000_0000 Definition: Horizontal Line Carry Value register Bit Descriptions: RSVD: Reserved - Unknown during read LCARY: Line Carry - Read/Write When the Horizontal down counter counts down to the written LCARY value, a carry is sent to increment the Vertical counter.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide If the Offset value is 0x0, no offset is used and addressing proceeds normally. Other Video Registers Brightness 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 CMP CNT Address: 0x8003_0020 Default: 0x0000_0000 Definition: Brightness Control register.
VideoAttribs 31 30 29 28 27 26 25 24 23 22 RSVD 21 SDSEL 20 19 18 17 16 BKPXD DVERT DHORZ EQUSER INTRLC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT INTEN PIFEN CCIREN RSVD LCDEN ACEN INVCLK BLKPOL HSPOL V/CPOL CSYNC DATEN SYNCEN PCLKEN EN Address: 0x8003_0024 Default: 0x0000_0000 Definition: Video Signal Attributes register.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide DHORZ: Double Horizontal - Read/Write Writing DHORZ = ‘1’ forces the values of the defined bitfields in the HClkTotal, HSyncStrtStop, HActiveStrtStop, HBlankStrtStop, and HClkStrtStop registers to be doubled (2X programmed value) when used.
V_CSYNC --> D7 (Smart Panel) HSYNC --> D6 7 BLANK --> D5 P17 --> D4 P3 --> D3 P[2:0] --> D[2:0] SPCLK --> E A Smart Panel has an integrated controller and frame buffer. Smart Panel R/W and RS signals must be implemented via GPIOs and controlled via software.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 1 - Pixel data output changes on falling edge of the clock on the SPCLK pin 7 BLKPOL: Blank Polarity - Read/Write The value written to this bit selects the polarity of the blanking signal on the BLANK pin: 0 - BLANK is active LOW (default) 1 - BLANK is active HIGH HSPOL: Horizontal Sync Polarity - Read/Write The value written to this bit selects the polarity of the horizontal synchronization signal on the HSYNC pin:
PCLKEN: Pixel Clock Enable - Read/Write The value written to this bit selects whether the pixel clock or smart panel clock are output to the SPCLK pin, or not: 0 - SPCLK pin at high impedance 1 - PCLK or SCLK active on SPCLK pin The PIFEN bit above selects PCLK vs. SCLK.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide ACRate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD RATE Address: 0x8003_0214 Default: 0x0000_0000 Definition: AC Toggle Rate register Bit Descriptions: RSVD: Reserved - Unknown during read RATE: Rate - Read/Write The RATE field must be written with a value that is one less than the number of horizontal video lines before the AC LC
This field should be written with a value that specifies the number of words that the FIFO empties before the FIFO requests that it be refilled. Values greater than 16 should be used with extreme caution as they can cause the Raster Engine to underflow, causing video jitter or other visual defects.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Writing a Dual Scan value to this bit selects whether the display is used in single scan mode, or dual scan mode where the display is divided into a ‘top’ half and a ‘bottom’ half. In dual scan mode, the video frame buffer in SDRAM must be organized such that ‘top’ and ‘bottom’ pixels alternate in consecutive locations. ‘Top’ and ‘bottom’ pixels are fetched and input to the Raster Engine’s video pipeline.
Table 7-14. Blink Mode Definition Table (Continued) M3 M2 M1 M0 Blink Mode 0 1 0 1 Blink to offset color single value mode 0 1 1 0 Blink to offset color 888 mode (555,565) 0 1 1 1 Undefined 1 1 0 0 Blink dimmer single value mode 1 1 0 1 Blink brighter single value mode 1 1 1 0 Blink dimmer 888 mode (555,565) 1 1 1 1 Blink brighter 888 mode (555,565) S: 7 Shift - Read/Write The Shift Mode is specified by selecting a value from Table 7-15 and writing it to this field.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Table 7-16.
P3 --> D3 P[2:0] --> D[2:0] 7 SPCLK --> E Smart Panel R/W and RS signals must be implemented via GPIOs and controlled via software. ParllIfIn 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 13 12 21 20 19 18 ESTRT 11 10 9 8 7 6 17 16 1 0 CNT 5 RSVD 4 3 2 DAT Address: 0x8003_005C Default: 0x0000_0000 Definition: Parallel Interface Output/Control Register This register, if PIFEN = ‘1’ in the VideoAttribs register, is used to access a Smart Panel.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Smart Panel R/W and RS signals must be implemented via GPIOs and controlled via software. The difference between the CNT[3:0] value and the ESTRT[3:0] value is what guarantees set up time for these GPIO signals to the Smart Panel before the rising edge of the E enable signal on the E pin.
Blink Control Registers 7 BlinkRate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD RATE Address: 0x8003_0040 Default: 0x0000_0000 Definition: Blink Rate Control register Bit Descriptions: RSVD: Reserved - Unknown during read RATE: Rate - Read/Write The blink rate value that is written to this field controls the number of video frames that occur before the LUT addresses assigned to ‘blink’ change between masked and unma
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Bit Descriptions: 7 RSVD: Reserved - Unknown during read MASK: Mask - Read/Write The Blink Mask value that is written to this field is logical ANDed, ORed, or XORed with the pixel data that addresses the LUT. The mask allows a blinking pixel to jump from the normal color definition location to a blink color definition location in the look-up-table.
PattrnMask 31 30 29 28 27 26 25 24 23 22 21 20 RSVD 15 14 13 12 19 18 17 16 3 2 1 0 PMASK 11 10 9 8 7 6 5 4 PMASK Address: 0x8003_004C Default: 0x0000_0000 Definition: Blink Pattern Mask register Bit Descriptions: RSVD: Reserved - Unknown during read PMASK: Pattern Mask - Read/Write The Blink Pattern Mask value that is written to this field defines which bits of the PATRN field in the BlinkPattrn register are used to validate a blink pixel: 0 - Bit used for comparison
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Bit Descriptions: 7 RSVD: Reserved - Unknown during read BGOFF: Background Off - Read/Write The function of Background Off value that is written to this field is defined by the selected blink mode. When the value of the M field in the PixelMode is written to select ‘blink to background’ mode, the BGOFF field defines a 24-bit color for the background.
CursorAdrReset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 ADR 15 14 13 12 11 10 9 8 ADR NA Address: 0x8003_0064 Default: 0x0000_0000 Definition: Cursor Image Address Reset register Bit Descriptions: ADR: Address - Read/Write The Cursor Address Reset value that is written to this field specifies the SDRAM location of the part of the cursor that will be displayed next after reaching the last line of the cursor.
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide CursorSize 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 DLNS 10 9 8 CSTEP CLINS CWID Address: 0x8003_0068 Default: 0x0000_0000 Definition: Cursor Height, Width, and Step Size register Bit Descriptions: RSVD: Reserved - Unknown during read DLNS: Dual Scan Lower Half Lines - Read/Write If DSCAN = ‘1’ in the PixelMode register, the Dual Scan Low
00 - Display 1 word (16 pixels) 01 - Display 2 words (32 pixels) 7 10 - Display 3 words (48 pixels) 11 - Display 4 words (64 pixels) CursorColor1, CursorColor2, CursorBlinkColor1, CursorBlinkColor2 31 30 29 28 27 26 25 24 23 22 21 20 RSVD 15 14 13 12 19 18 17 16 3 2 1 0 COLOR 11 10 9 8 7 6 5 4 COLOR Address: CursorColor1 - 0x8003_006C CursorColor2 - 0x8003_0070 CursorBlinkColor1 - 0x8003_021C CursorBlinkColor2 - 0x8003_0220 Default: 0x0000_0000 Definition: Cursor Colo
77 7 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide CursorXYLoc 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 CEN 13 21 20 19 18 17 16 4 3 2 1 0 YLOC 12 11 10 9 8 7 6 RSVD 5 XLOC Address: 0x8003_0074 Default: 0x0000_0000 Definition: Cursor X and Y Location register Bit Descriptions: RSVD: Reserved - Unknown during read YLOC: Y Location - Read/Write The Y Location value written to this field specifies the starting vertical Y location of
The X Location value written to this field specifies the starting horizontal X location of the cursor image. The value is compared to the horizontal pixel counter and it should be specified to be between the active start and active stop horizontal pixel values. 7 This X Location value is also used to specify the starting location for the cursor image in the upper half of the display when Dual Scan mode is enabled by writing DSCAN = ‘1’ in the PixelMode register.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide When Dual Scan mode is enabled by writing DSCAN = ‘1’ in the PixelMode register, the Y Location value written to this field specifies the starting vertical Y location (in the lower half of the display) of the cursor image. The value is compared to the vertical line counter and it should be specified to be between the active start and active stop vertical line values.
When EN = ‘0’ and the 2-bit cursor pixel fetched from SDRAM is ‘10’, CursorColor1, is used for the non-blinking cursor image. When EN = ‘0’ and the 2-bit cursor pixel fetched from SDRAM is ‘11’, CursorColor1, is used for the non-blinking cursor image. RATE: Rate - Read/Write When EN = ‘1’, the Rate value written to this field specifies the number of video frames that will occur before switching between CursorColor1 or CursorColor2, and CursorBlinkColor1 or CursorBlinkColor2, respectively.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Writing a Frame Counter Selection value to this bit selects which Frame Counter is used for the current 3-bit pixel value: 7 0 - use FRAME_CNT3 1 - use FRAME_CNT4 This bit is only defined for address locations GrySclLUTx Base + 0x000 to GrySclLUTx Base + 0x01C.
Writing ‘1’s to these Matrix Position Enable bits enables the control/dither of the monochrome data outputs according the to horizontal position, the vertical position, the frame, and the 3-bit incoming pixel value. Please reference Table 7-17 below to determine D bit positions in the matrix. Table 7-17.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Where: FRAME[1:0] = FRAME_CNT3 or FRAME_CNT4 as defined by FRAME at address Pixel_In 7 VCNT[1:0] = VERT_CNT3 or VERT_CNT4 as defined by VERT at address Pixel_In HCNT[1:0] = HORZ_CNT3 or HORZ_CNT4 as defined by HORZ at address Pixel_In LUTSwCtrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 SSTAT SWTCH RSVD 15 14 13 12 11 10 9 8 RSVD Address: 0x8003_0218 Default: 0x00
ColorLUT 31 30 29 28 27 26 25 24 23 22 21 20 RSVD 15 14 13 12 19 18 17 16 3 2 1 0 R 11 10 9 8 7 6 5 4 G B Address: 0x8003_0400 through 0x8003_07FC Default: Unknown after power up Definition: Color Look-Up-Table Bit Descriptions: Note: Triple 8-bit RGB is the most common way to use the LUT. However, The LUT may be organized differently depending on the needs of the display technology.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Bit Descriptions: 7 RSVD: Reserved - Unknown during read SIGVAL: Signature Results Value - Read ONly The Signature Results Value contained in this field is the 16-bit result of the video output signature calculation. This Signature Results Value is usually updated once per frame based on the SigClrStr location. During grayscale operation, the Signature Results Value is updated once every 12 frames.
CLKEN: Clock Enable - Read/Write Writing a ‘1’ to this bit enables the CLKEN control for calculation in the video signature. 7 Writing a ‘0’ to this bit disables the CLKEN control for calculation in the video signature. BLANK: Blank - Read/Write Writing a ‘1’ to this bit enables the BLANK output for calculation in the video signature. Writing a ‘0’ to this bit disables the BLANK output for calculation in the video signature.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide Bit Descriptions: 7 RSVD: Reserved - Unknown during read STOP: Stop - Read/Write The STOP value is the value of the Vertical down counter at which the VSIGEN signal becomes inactive (stops).This indicates the end of the signature calculation for the Vertical frame. VSIGEN is an internal block signal. The SIG_ENABLE control to the video signature analyzer is enabled by the logical AND of VSIGEN and HSIGEN.
The STRT value is the value of the horizontal down counter at which the HSIGEN signal becomes active (starts). This indicates the start of the signature calculation for a horizontal line. HSIGEN is an internal block signal. The SIG_ENABLE control to the video signature analyzer is enabled by the logical AND of VSIGEN and HSIGEN.
77 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 7 7-82 DS785UM1 Copyright 2007 Cirrus Logic
8Graphics Accelerator 8.1 Overview Note: The chapter applies only to the EP9307 and EP9315 procesors. The hardware Graphics Accelerator improves graphic performance by handling block copy, block fill, and hardware line draw functions. The Graphics Accelerator is used to off-load graphics functions from the ARM Core. Pixel depths supported by the Graphics Accelerator are 4, 8, 16 or 24 bits per pixel.
88 Graphics Accelerator EP93xx User’s Guide 8.2.1 Copy 8 It is possible to copy data from the source memory to the destination memory using the copy form of block transfer. A copy is accomplished by not enabling any of the data path options, i.e. Transparency, Logical Mask, or Destination Mask. 8.2.1.1 Transparency Transparency is used to preserve pixels in the destination memory.
2. Logical Destination 3. Transparency 88 Graphics Accelerator EP93xx User’s Guide 8 8.2.2 Remapping The Graphics Accelerator supports single bit pixel remapping with foreground/background or foreground/transparency to system color depth images (1 bpp mapped to 4, 8, 16 or 24 bpp expansion.) Images stored as a single bit plane can be expanded with a foreground color and either transparent or background color.
88 Graphics Accelerator EP93xx User’s Guide 8.3.1 Breshenham Line Draws 8 Based on Breshenham's algorithm, this is the fastest of the two lines draws. Patterned lines drawn are aligned to the major axis. Steps made in the major axis are made on a 4095/4096 pixel step per clock basis. This allows the algorithm to complete the line with the amount of pixel draws in the major axis. Steps in the minor axis are made in sub pixel increments. Patterned lines drawn in this mode are aligned to the major axis.
8.4.1 Memory Organization for 1 Bit Per Pixel (bpp) The 1 bpp storage format is for storing compressed image data for remapping only. This data cannot be displayed until it is remapped into a supported color depth. Table 8-2 shows how compressed 1 bpp images are stored in memory as 8 pixels per byte. Table 8-2. bpp Memory Organization 31 24 23 16 15 8 7 0 0x0000 P(7,3)....... ......P(0,3) P(7,2)....... ......P(0,2) P(7,1)....... ......P(0,1) P(7,0)....... ......P(0,0) 0x0004 X P(7,5)....... ...
88 Graphics Accelerator EP93xx User’s Guide Table 8-4. 8 bpp Memory Organization 8 31 24 23 16 15 8 7 0 0x0000 P(3,0) P(2,0) P(1,0) P(0,0) 0x0004 P(7,0) P(6,0) P(5,0) P(4,0) 0x0008 P(3,1) P(2,1) P(1,1) P(0,1) 0x000C P(7,1) P(6,1) P(5,1) P(4,1) 0x0010 P(3,2) P(2,2) P(1,2) P(0,2) 0x0014 P(7,2) P(6,2) P(5,2) P(4,2) ..... ..... ..... ..... ..... 0x0028 P(3,5) P(2,5) P(1,5) P(0,5) 0x002C P(7,5) P(6,5) P(5,5) P(4,5) 8.4.
8.4.5 Memory Organization for 24-Bits Per Pixel The 24 bpp packed or unpacked storage formats can be used to support higher color displays. These modes would typically be used to implement an 8-bit blue, 8-bit green, 8-bit red color scheme. Table 8-6 shows how 24 bpp packed images are stored in memory as 1 pixel for every three bytes. Table 8-7 shows how 24 bpp unpacked images are stored in memory Table 8-6.
88 Graphics Accelerator EP93xx User’s Guide Table 8-7. 24 bpp Unpacked Memory Organization (1 pixel/ 1 word) 8 0x00B0 unused P(4,5)R P(4,5)G P(4,5)B 0x00B4 unused P(5,5)R P(5,5)G P(5,5)B 0x00B8 unused P(6,5)R P(6,5)G P(6,5)B 0x00BC unused P(7,5)R P(7,5)G P(7,5)B 8.4.6 Memory Map Access The Graphics Accelerator has access to the entire memory map. Therefore pixel block function processing is not limited to graphics and video memory. Font storage, bit map storage, etc.
Table 8-9. Transfer Example 2 Address 31 0x0000 0x000C FF 0 EE DD CC 31 BB 0 AA 99 88 31 77 0 66 55 44 31 33 8 0 22 11 00 If a Block Copy starts at pixel 3 and 10 pixels are to be copied, the “BLKSRCWIDTH” register would be loaded with 0x3 (4 words - 1 word = 0x3). The pixels fetched are highlighted in Table 8-10. Table 8-10. Transfer Example 3 Address 31 0x0000 0x000C FF 0 EE DD CC 31 BB 0 AA 99 88 31 77 0 66 55 44 31 33 0 22 11 00 8.5.1.
88 Graphics Accelerator EP93xx User’s Guide memory and the other register, “DESTPIXELSTRT”, is used for the destination memory. All start and stop values described below apply for source and destination values. 8 The two registers operate in an identical fashion for source and destination. To see how they operate requires looking at several tables that show the memory layout for pixels in the various color modes. 8.5.2.
8.5.2.2 8 BPP Word Layout For a Block Copy where 4 pixels are transferred per scan line, let the starting SDRAM address of the source image be 0x0000. Table 8-15 shows that Pixel 2 starts at bit 16, Pixel 3 starts at bit 24, etc. The start pixel, P2, is in the word at address 0x0000 and has a beginning bit position of 16. This makes 16 = 0x10 the value that is used for the SPEL field in the “SRCPIXELSTRT” register. Table 8-15.
88 Graphics Accelerator EP93xx User’s Guide Let the starting SDRAM address of the destination image be 0x0044. Table 8-18 shows that Pixel 0 starts at bit 16. The start pixel, P0, is in the word at address 0x0044 and has a beginning bit position of 16. This makes 16 = 0x10 the value that is used for the SPEL field in the “DESTPIXELSTRT” register. 8 The end pixel, P7, is in the word at address 0x0054 and has a beginning bit position of 0.
Note:The word count for this example would be: 6 - 1 = 5 words, since P6 ends in the 6th word. The word count takes into account the whole pixel, not just the starting location. So, WIDTH = 0x5 would be written to the “BLKDESTWIDTH” register. 8 Table 8-20. 24 BPP Memory Layout for Destination Image Address 31 24 23 16 15 8 7 0 0x0058 P1 P0 P0 P0 0x005C P2 P2 P1 P1 0x0060 P3 P3 P3 P2 0x0064 P5 P4 P4 P4 0x0068 P6 P6 P5 P5 0x006C P7 P7 P7 P6 8.
88 Graphics Accelerator EP93xx User’s Guide 3. Setup DESTLINELENGTH Register A. Determine how many pixels occupy a 32-bit word. For example, four 8-bit pixels can occupy a 32-bit word. 8 B. Determine the width of the display in pixels. For example, a 640x480 display has a width of 640 pixels. C. The line length is determined by the ‘stride’ of the display, that is, how many 32-bit words are needed to populate the width of the display with pixels.
9. Setup BLKDESTWIDTH Register Write ‘abs(X2 -X1) modulo 4096, minus 1’ to the WIDTH field in the “BLKDESTWIDTH” register. 10.Setup BLKDESTHEIGHT Register Write ‘abs(Y2 - Y1) / 4096, minus 1’ to the HEIGHT field in the “BLKDESTHEIGHT” register. 11.Setup BLOCKCTRL Register A. Clear the “BLOCKCTRL” register by writing 0x0000_0000 to it. B. Set the LINE bit to ‘1’ C. If X2 > X1, set the DXDIR bit to ‘1’, else set the DXDIR bit to ‘0’ D. If Y2 > Y1, set the DYDIR bit to ‘1’, else set the DYDIR bit to ‘0’ E.
88 Graphics Accelerator EP93xx User’s Guide SPEL = [X2% 2 (pixel depth / 8-bit byte)] x 8 = [101% 2 (16-bits / 8-bits)] x 8-bits = [101% 2] x 8 = 1 x 8 = 8 = 0x8, and 8 EPEL = [X1% 2 (pixel depth / 8-bit byte)] x 8 = [20% 2 (16-bits / 8-bits)] x 8-bits = [20% 2] x 8 = 0 x 0 = 0 = 0x0 5. Write the word-aligned value of the SDRAM address ‘for the beginning of the line draw’ to the “BLKDESTSTRT” register. 6. Write the desired background color value to the BG field in the “BACKGROUND” register.
SPEL is the starting pixel position within the word that the pixel-fill will begin with. EPEL is the ending pixel position within the word that the pixel-fill will end with. See Section 8.5.2. Pixel End And Start. Use the DESTPIXELSTRT calculation in the block copy example shown in Section 8.6.4.1. 3. Setup DESTLINELENGTH Register Write the line length value to the LEN field in the “DESTLINELENGTH” register, where LEN is determined by: A. Find how many pixels occupy a 32-bit word.
88 Graphics Accelerator EP93xx User’s Guide 7. Setup BLOCKCTRL Register For (example) 16-bit pixels and Mask AND Mode: 8 A. Clear the “BLOCKCTRL” register by writing 0x0000_0000 to it B. Write Fill = ‘1’, BG = ‘0’, M = 0x1, P = 0x4, and INTEN = ‘1’ to the “BLOCKCTRL” register C. Write EN = ‘1’ to the “BLOCKCTRL” register 8. Wait for an Interrupt or Poll for EN = ‘0’ in the BLOCKCTRL Register. When the EN bit becomes cleared to ‘0’, the Block Fill Algorithm function is complete. 8.6.
comprise the first scan line of the source image. For example, Table 8-21 shows that six 32-bit words are needed to contain six 24bit pixels. So, LEN = 6 - 1 = 5 = 0x5. Table 8-21. Words Needed for Six 24-Bit Pixels Address 31 24 23 16 15 8 7 0 0x0000 P1 P0 P0 P0 0x0004 P2 P2 P1 P1 0x0008 P3 P3 P3 P2 0x000C P5 P4 P4 P4 0x0010 P6 P6 P5 P5 0x0014 P7 P7 P7 P6 2. Setup Destination Memory A.
88 Graphics Accelerator EP93xx User’s Guide refer to the note in Section 8.5.2.4 on page 8-12. E. Write the desired value to the HEIGHT field in the “BLKDESTHEIGHT” register, where HEIGHT = the height in lines of the image that is to be copied minus 1. 8 For example, a 20-pixels x 10-lines image has a height of 10 lines. So, HEIGHT = 10 - 1 = 9 = 0x9. F. The “BLOCKCTRL” register must be cleared to 0x0. This action clears out the previous graphics instruction.
8.6.4.1 Example of Block Copy To achieve the following display and pattern, follow Steps A to I in this section. 8 • Screen Size is 640x480x16-bits/pixel • Screen memory starts at physical address 0x0000_0000 • Image to be copied is at physical address 0x0000_0960 • Image to be copied is at position (51, 75) • Image destination is at position (300, 115) • Source and destination width is 30 pixels A. SRCPIXELSTRT = (51 * 16)% 32 = 16 B. BLKSRCSTRT = 0x960 C.
88 Graphics Accelerator EP93xx User’s Guide 8.7 Registers Table 8-22.
Register Descriptions 8 SRCPIXELSTRT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD PEL Address: 0x8004_0000 - Read/Write Default: 0x0000_0000 Mask: 0x0000_001F Definition: Source Pixel Start register Bit Descriptions: RSVD: Reserved - Unknown during read PEL: Source Pixel Location - Read/Write For the starting pixel (at the starting X-Y coordinate of the 1st scan line) of the source image for a block copy, the
88 Graphics Accelerator EP93xx User’s Guide 8 Default: 0x0000_0000 Mask: 0x001F_001F Definition: Destination Pixel Start/End register Bit Descriptions: RSVD: Reserved - Unknown during read EPEL: Destination Pixel Location - Read/Write For the ending pixel (at the ending X-Y coordinate of the 1st scan line) of the destination image for a block copy, the value in this field specifies where the beginning bit of the ending pixel is located in a 32-bit word.
Default: 0x0000_0000 Mask: 0xFFFF_FFFC Definition: Block Source Word Address Start register 8 Bit Descriptions: ADR: Address - Read/Write The value in this field specifies the word address of the SDRAM frame buffer location that contains the starting pixel (of the first scan line) of the source image. The ADR field and the PEL field in the “SRCPIXELSTRT” register together define the starting pixel’s address in the SDRAM frame buffer of the source image.
88 8 Graphics Accelerator EP93xx User’s Guide BLKSRCWIDTH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD WIDTH Address: 0x8004_0010 - Read/Write Default: 0x0000_0000 Mask: 0x0000_0FFF Definition: Block Function Source Width Register Bit Descriptions: RSVD: Reserved. Unknown during read.
The value in this field specifies the number of 32 bit words, minus 1, that are needed to contain all of the pixels that comprise width of the display. The value of LEN is determined by: 1) Find how many pixels occupy a 32-bit word. For example, four 8-bit pixels can occupy a 32-bit word. 2) Find the width of the display in pixels. For example, a 640x480 display has a width of 640 pixels.
88 Graphics Accelerator EP93xx User’s Guide For Line Draw functions, the method to determine the value of WIDTH is dependent on the line draw algorithm. For the Burnishing algorithm, please refer to BLKDESTWIDTH in Section 8.6.1 on page 8-13. For the DX/DY algorithm, please refer to BLKDESTWIDTH in Section 8.6.3 on page 8-16. The value of WIDTH is multiplied by the value of HEIGHT in the BLKDESTHEIGHT register to determine the number of line draw iterations.
DESTLINELENGTH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD LEN Address: 0x8004_0020 - Read/Write Default: 0x0000_0000 Mask: 0x0000_0FFF Definition: Block Destination Line Length Register Bit Descriptions: RSVD: Reserved - Unknown during read LEN: Length - Read/Write The value in this field specifies the number of 32 bit words, minus 1, that are needed to contain all of the pixels that comprise width of the dis
88 8 Graphics Accelerator EP93xx User’s Guide BLOCKCTRL 31 30 29 28 27 26 25 24 23 22 21 RSVD 20 19 PACKD 18 17 P 16 ERROR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTEOI BG REMAP D1 D0 M1 M0 SYDIR SXDIR DYDIR DXDIR LINE FILL TRANS INTEN EN Address: 0x8004_0024 - Read/Write Default: 0x0000_0000 Mask: 0x001F_FFFF Definition: Block Function Control Register Bit Descriptions: RSVD: Reserved - Unknown during read PACKD: Packed Image Bit - Read/Write
Table 8-23. Pixel Mode Encoding P2 P1 P0 Pixel Mode 0 1 1 not defined 1 0 0 16 bits per pixel 1 0 1 not defined 1 1 0 24 bits per pixel packed 1 1 1 32 bits per pixel (24 bpp unpacked) ERROR: 8 Error Indicator - Read/Write 1 - Bus error has occurred 0 - No error. INTEOI: Interrupt / End of Interrupt - Read/Write Reading this bit returns the status of the Block Fill or Block Copy function interrupt (active high): ‘1’ - Interrupt request.
88 Graphics Accelerator EP93xx User’s Guide ‘1’ - Pixel Expansion Mapping Function enabled ‘0’ - Pixel Expansion Mapping Function disabled 8 The Pixel Expansion Mapping Function converts single bit pixels in the source image to defined pixel-depth (see Table 8-23) pixels in the destination image. When BG = ‘0’, source image pixels are unaffected (transparent) when they are copied to the destination image.
DYDIR = ‘0’ - Down in Y 8 For a Line Draw function: DXDIR = ‘1’ - If X2 > X1 DXDIR = ‘0’ - If X2 <= X1 DYDIR = ‘1’ - If Y2 > Y1 DYDIR = ‘0’ - If Y2 <= Y1 LINE: Line Draw Function Enable - Read/Write ‘0’ - Line draw disabled ‘1’ - Line draw enabled Reading this bit returns a valid value only when EN = '1'. FILL: FILL Function Enable - Read/Write ‘0’ - Fill disabled ‘1’ - Fill (with mask value) enabled Reading this bit returns a valid value only when EN = '1'.
88 8 Graphics Accelerator EP93xx User’s Guide TRANSPATTRN 31 30 29 28 27 26 25 24 23 22 21 20 RSVD 15 14 13 12 19 18 17 16 3 2 1 0 PATRN 11 10 9 8 7 6 5 4 PATRN Address: 0x8004_0028 - Read/Write Default: 0x0000_0000 Mask: 0x00FF_FFFF Definition: Block Function Transparency Pattern Register Bit Descriptions: RSVD: Reserved - Unknown during read PATRN: Transparent Bit Pattern - Read/Write The value in this field specifies a transparent bit pattern.
MASK: Mask - Read/Write For a Block Copy function, the value in this field specifies the logical mask, if used. If BG = ‘1’, M = ‘00’, and REMAP = ‘1’ in the BLOCKCTRL register, the value specifies the destination foreground color for source image pixels = ‘1’. For Block Fill and Line Draw functions, the value in this field specifies the pixel color for the destination image. The mask or color value is located in the least significant BPP part of the register for modes less than 24 bpp.
88 8 Graphics Accelerator EP93xx User’s Guide LINEINC 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 21 20 19 18 17 16 5 4 3 2 1 0 YINC 13 12 11 10 9 8 7 6 RSVD XINC Address: 0x8004_00343 - Read/Write Default: 0x0000_0000 Mask: 0x0FFF_0FFF Definition: Line Draw Increment Register Bit Descriptions: RSVD: Reserved - Unknown during read YINC: Y Increment - Read/Write The value in this field specifies a 12-bit binary fraction of a pixel to be accumulated in the vertic
Bit Descriptions: RSVD: Reserved - Unknown during read YINIT: Y Initialization - Read/Write 8 The value in this field specifies a 12 bit binary fraction of a pixel that provides sub-pixel precision to the algorithm. The minimum fractional value is 1/4096. This field can also be initialized to account for truncation errors in the drawing algorithm.
88 Graphics Accelerator EP93xx User’s Guide If BG = ‘1’ in the BLOCKCTRL register, a ‘0’ causes a pixel fill from the BACKGROUND register. If BG = ‘0’ in the BLOCKCTRL register, a ‘0’ is transparent. 8 When drawing solid lines, write LINEPATTERN = 0x000F_FFFF.
91/10/100 Mbps Ethernet LAN Controller 9.1 Introduction The Ethernet LAN Controller incorporates all the logic needed to interface directly to the AHB and to the Media Independent Interface (MII). It includes local memory and DMA control, and supports full duplex operation with flow control support. Figure 9-1 shows a simplified block diagram. This block was designed with a RAM of 544 words, each word containing 33 bits. These RAMs are used for packet buffering and controller data storage.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide The Descriptor Processor implements the Hardware Adapter Interface Algorithm and generates transfer requests to the AHB Interface Controller. The back-end interfaces to the MAC controllers and services MAC requests to run accesses to the FIFO and update queue status. The Descriptor Processor also generates internal requests for descriptor fetches.
The RAM blocks are interleaved in the AHB address space. AHB address bits 0 and 1 are byte selects and must be zero for direct access. AHB address bit 2 selects the left or right RAM array, which is the Transmit or Receive array. AHB address bits 3,4, and 5 perform a 1of-8 column select. Address bit 6 selects the even or odd row address. Address bits 7, 8, 9, and 10 decode the rows. Thus from an AHB addressing perspective, the MAC FIFOs are one large RAM array.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide E th e rn e t F ra m e /P a c k e t F o rm a t (T y p e II, o n ly ) 9 Packet F ra m e up to 7 bytes alternating 1s / 0s 1 byte 6 bytes 6 bytes SFD DA SA p re am b le 2 bytes optional field N bytes LL C da ta M bytes 4 bytes Pad FCS fra m e le n g th m in 6 4 b y te s m a x 1 5 1 8 b yte s D ire c tio n o f T ra n s m is sio n S F D = S ta rt o f F ra m e D e lim ite r D A = D e s tin a tio n A d d re s s S A = S o u rc e A
9.1.3 Packet Transmission Process This section explains the complete packet transmission process as seen on the Ethernet line. This process includes: carrier deference, back-off, packet transmission, transmission of EOF, and SQE test. Refer to Figure 9-3.The Packet Transmission Process Start of Transmit Frame in fifo Carrier Deference Carrier Deference is detailed in the next diagram. Transmission ends with either completion of the frame, or a collision.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Complete state. Thus, the Carrier Deference state may be entered and exited immediately, or there may be a delay depending on the state when entered. 9 When this Carrier Deference state diagram is entered from the Packet Transmission Process, the entry may be to any state shown. The Packet Transmission Process exits this state diagram ONLY from IFG Complete.
9.1.4 Transmit Back-Off Refer to Figure 9-3. Once transmission is started, either the transmission is completed, or there is a collision. There are two kinds of collision: normal collision (one that occurs within the first 512 bits of the packet) and late collision (one that occurs after the first 512 bits). In either collision type, the MAC engine always sends a 32 bit jam sequence, and stops transmission. After a normal collision and the jam, transmission is stopped, or “backed-off”.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide The resultant 32 bit field is transmitted on the line with bit X31 first through X0 last. 9.1.4.3 Bit Order In compliance with ISO/IEC 8802-3 section 3.3, each byte is transmitted low order bit first, except for the CRC, as noted in Section 9.1.4.2 on page 9--7. D0 D7 D8 D15 D16 D31 Byte Half-Word Word Direction of transmission Figure 9-5. Data Bit Transmission Order 9.1.4.
9.1.4.6 Hash Filter The 64 bit Logical Address Filter provides DA filtering hashed by the CRC logic. The Logical Address Filter is sometimes referred to as the multicast address filter. Referring to Figure 9-6, notice that the CRC computation starts at the first bit of the frame, which is also the first bit of the DA. (Recall that a “frame” is a “packet” without the preamble.) The CRC Logic can be viewed as a 32 bit shift register with specific Exclusive-OR feedback taps.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide The relationship of RXCtl.MA and RXCtl.IAHA is shown below. 9 Table 9-2. RXCtl.MA and RXCtl.IAHA[0] Relationships RXCtl.MA RXCtl.IAHA[0] 0 0 Hash filter not used in acceptance criteria. Hash Filter Acceptance Results 1 0 All multicast frames (first bit of DA = 1) passing the hash are accepted. 0 1 All individual address frames (first bit of DA = 0) passing the hash are accepted. 1 1 All frames that pass the hash are accepted. 9.
To comply with the standard, pause frames should only be sent on full duplex links. The MAC does not enforce this, it is left to the driver. If a pause frame is sent on a half duplex link, it is subject to the normal half duplex collisions rules and retry attempts.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide most PHYs require a preamble for access to the PHY's registers. However, to be safe, check PHY's data sheet to determine if a preamble is needed to read/write PHY registers. 9.1.4.11.1 Steps for Reading From the PHY Registers. 1. Read the value from the SelfCtl Register. 2. Since most PHYs need a Preamble for the MAC to read/write the PHY registers, you may need to clear the PreambleSuppress bit. 3.
9.1.4.11.4 Steps for PHY Startup 1. Set the MDC ClockDivisor and the PreambleSuppress for the PHY in the SelfCtl register. The default value 0x0000_0F10 is appropriate for most PHYs in transmission mode. 2. Have the PHY perform auto-negotiation. 3. Read the Auto-Negotiation_Link_Partner_Ability register to check the PHY’s configuration. 4. If the link is Full Duplex, then set MAC for Full Duplex. 9.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide of buffers as they are exchanged with the MAC. When the MAC reads a descriptor, it keeps a copy of the index, which it includes in any status entry associated with that buffer. The Not Start Of Frame bit may be set by the Host on any buffer in which it does not want a new frame to be started. This buffer would then only be used for chaining of frame fragments.
Receive Descriptor Format - First Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 BA 15 14 13 12 11 10 9 8 BA Definition: Receive Descriptor, first word. Contains the base address to the data buffer. Bit Descriptions: BA: Buffer Address. This location holds the 32 bit address pointer to the data buffer, this must point to a word aligned location.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9.2.3 Receive Status Queue 9 The receive status queue is used to pass receive status from the MAC to the Host. In operation, the receive status queue is similar to the receive descriptor queue. It is a circular queue in contiguous memory space. The location and size of the queue are set at initialization by writing to the Receive Status Queue Base Address and the Receive Status Queue Base Length registers.
Receive Status Queue 9 bits 31 - 0 RStatQ 0 R F P R F P R F P R F P RStatQ 1 Receive Status queue Base Address (32) (RxSBA) RStatQ c R S tatQ j Receive Status Current Address(32) (RxSCA) RStatQ c+1 c = current frame R F P R F P R F P R F P R F P R F P Status (31) Buffer Index (15) Frame Length (16) Status (31) Buffer Index (15) Frame Length (16) Status (31) Buffer Index (15) Frame Length (16) Receive Status queue Base Length (16) (RxSBL) Status (31) Buffer Index (15) Frame Length (16)
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide If both EOF and EOB bits are zero, the entry was made for a receive header threshold. This indicates that there have been at least as many bytes transferred as specified in Receive Header Length 1 or 2. These registers may be set to any threshold to provide an early indication to the Host that a receive frame is in progress.
EOF: End Of Frame. When this bit is set, the associated buffer contains the last data associated with this frame. In the case of an extra data or overrun error, the buffer may not contain the actual end of frame data. For a receive header status the EOF and EOB bits will both be clear. EOB: End Of Buffer. When this bit is set, no more data will be transferred to the associated data buffer. This may be due to an end of frame transfer or to reaching the actual end of the buffer.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide HTI: Hash Table Index. If the frame was accepted as a result of a hash table match, these bits contain the hash table index, otherwise they are written as zero. If the frame was received as a result of Promiscuous Accept, this field will be zero.
9.2.3.2 Receive Flow 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9 10 Protocol Stack RECV Call Device Driver 1 Receive Descriptor Queue Receive Frame Data Receive Status Queue 11 Memory 3 2 System Memory AHB PCI Bus 8 7 Receive Descriptor Registers 4 Receive Descriptor Processor 9 6 RxDEQ MAC Engine RxSEQ CS 8950 12 5 LAN Medium Figure 9-9.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Refer to the circled numbers in Figure 9-9. The detailed receive flow is: 1. Driver initializes some number of receive descriptors. 9 2. Driver writes RXDEnq register with the additional number of receive descriptors. 3. On-chip Descriptor Processor fetches descriptors into internal FIFO decrements RXDEnq appropriately. 4. The address of the next receive data buffer is loaded into the Receive Buffer Current Address. 5.
9.2.3.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9.2.3.
9.2.3.6 Receive Frame Pre-Processing The MAC pre-processes all incoming receive frames. First the frame is either passed on to the next level or discarded according to the destination address filter. The next decision is whether to accept the frame. A frame is accepted when the frame data are brought into MAC through internal memory. The final step in frame pre-processing is the decision on causing an interrupt. These pre-processing steps are detailed in Figure 9-12.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9.2.3.7 Transmit Descriptor Processor Queues The transmit descriptor processor uses two circular queues in Host memory to manage the transfer of transmit data frame. The transmit descriptor queue is used to pass descriptors of user's data buffers from the Host to the MAC. The transmit status queue is used to pass information on the MAC's use of the data buffer back to the Host.
9 Transmit Descriptor Format and Data Fragments register sizes are in bits, and shown in parentheses ().
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9 Example: Fragments 0, 1, 2 make-up one complete frame. register sizes are in bits, and shown in parentheses ().
Bit Descriptions: TBA: Transmit Buffer Address. The transmit buffer address contains the 32 bit address pointer to the transmit buffer. The base address of the data buffer must be word-aligned (32-bit aligned). Transmit Descriptor Format - Second Word 31 30 29 28 27 26 25 24 EOF 15 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 TBI 14 AF 13 12 11 RSVD 10 9 8 7 TBL Definition: Transmit Descriptor, second word. Contains control, index and length for the descriptor.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide TBL: Transmit Buffer Length. This field contains the byte count of the number of bytes in the transmit buffer. There are no restrictions on the actual buffer size. If the length is set to zero, the descriptor will be ignored. A frame may not be terminated with a zero length buffer. 9 9.2.3.10 Transmit Status Queue The Transmit Status queue is used to pass transmit status from the MAC to the Host.
9 bits 31 - 0 Transmit Status Base Address (TxSBA) (32) Status 0 Status 1 Status 2 register sizes are in bits, and shown in parentheses (). Current Frame Status Transmit Status Current Address (TxSCA)(32) Next Status Position Status m 31 30 Frame Status (15) 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Buffer Index (15) TxWE = Transmitted Without Error TxFP = Transmit Frame Processed Figure 9-15.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9.2.3.11 Transmit Status Format Only one Transmit Status entry is posted for each transmit frame, regardless of the number of transmit descriptors that are used to describe the frame. 9 Transmit Status 31 30 29 28 27 26 25 24 TxFP TxWE FA LCRS RSVD OW TxU EColl 15 14 13 12 11 10 9 8 RSVD 23 22 21 20 19 RSVD 7 6 18 17 16 1 0 NColl 5 4 3 2 TBI Definition: Transmit Status.
NColl: Number of Collisions. This field contains the number of collisions that were experienced in transmitting this frame. TBI: Transmit Buffer Index. The transmit buffer index is a copy of the transmit buffer index from the first descriptor of a transmit frame. This is provided as an aid to the Host software in keeping track of the transmit buffers.
9.2.3.12 Transmit Flow 9 Protocol Stack XMIT Call 1 TX_Complete 11 Device Driver 2 Tx Descriptor Queue Transmit Frame Data Tx Status Queue 10 4 Memory 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 3 8 System Memory 9 PCI Bus AHB 6 Transmit Descriptor Registers TxDEQ 5 Transmit Descriptor Processor MAC Engine CS 8950 7 LAN Medium Figure 9-16.
Refer to Figure 9-16. The detailed transmit flow is: 1. Protocol stack initiates a transmit frame. 9 2. Driver parses protocol stack buffer into Transmit Descriptor Queue. 3. Driver writes number of additional entries to the Transmit Enqueue register. 4. On-chip Descriptor Processor fetches descriptor information. 5. On-chip Descriptor Processor initiates data move. 6. Frame data fetched from system memory into the transmit FIFO. 7. Frame transmitted onto LAN medium. Steps 6 and 7 can overlap. 8.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9.2.3.
9.2.4 Interrupts 9.2.4.1 Interrupt Processing Interrupts can be associated with on chip status or with off-chip status. (Off-chip status is status that has been transferred to either the transmit or receive status queue.) The status for any outstanding interrupt event is available via two different register addresses: IntStsP (Interrupt Status Preserve) and IntStsC (Interrupt Status Clear). Reading the IntStsP register has no effect on the bits set in the register.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 14.Wait for RxAct (BMSts) to be set, and then enqueue the receive descriptors and status. This will trigger bus master activity for the descriptor reads. 9 15.Set the required values for Individual Address and Hash Table. 16.Set the required options in RXCtl and TXCtl, enabling SRxON, and STxON. 17.Set any required options in the PHY, and activate. 18.Enqueue transmit descriptors as required. 9.2.5.
1. RxMiss - This bit indicates that the receive frames have been missed which may be the result of insufficient bus bandwidth being available, or of a lack of receive descriptors, or free receive status locations. 2. RxBuffers - This bit is a warning that the last free receive descriptor has been read by the controller, and RXDEnq is now zero.In a system with a dynamic number of receive buffers, this may be use as a trigger to allocate more buffers. 3.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 10.Wait for TxAct in BMSts to be set and then write the appropriate number of descriptors remaining in the queue to TXDEnq. 9.3 Registers Table 9-3.
Table 9-3.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Chip Reset: 0x0000_0x0x 9 Rx Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Receiver Control Register. The Receive Control register is reset by Rx Reset signal generated by holding the TESTSELn pin low. The same signal is also used to reset the receive MAC.
RxFCE1: Rx Flow Control Enable, bit 1. Setting the RxFCE1 bit causes all receive frames that pass the Individual Address [1] register to be scanned for flow control format and, if detected, the Transmit Flow Control Timer register is set appropriately. RxFCE0: Rx Flow Control Enable, bit 0. Setting the RxFCE0 bit causes all receive frames that pass the Individual Address [0] register to be scanned for flow control format and, if detected, the Transmit Flow Control Timer register is set appropriately.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide IAHA: Individual Address Hash Accept. When set, received frame are accepted when the DA is an Individual Address (first bit of DA = 0), that is accepted by the hash table. See Descriptor Processor Transmit Registers. IA3: Individual Accept 3. When set, received frames are accepted which the DA matches the Individual Address 3 Register. IA2: Individual Accept 2.
0x0000_0000 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Transmit Control Register. 9 Soft Reset: Definition: Bit Descriptions: RSVD: Reserved. Unknown During Read. DefDis: 2-part DefDis. Before a transmission can begin, the MAC follows a deferral procedure. With the 2-part DefDis bit clear, the deferral is the standard two-part deferral as defined in ISO/IEC 8802-3 paragraph 4.2.3.2.1. With the 2-part DefDis bit set, the two-part deferral is disabled.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide PB: Pause Busy: This bit remains set as long as a pause frame is being transmitted. Only one pause frame may be sent at any time, therefore the Send Pause and Pause Busy bits should be zero before a new pause frame is defined. STxON: Serial Transmit ON. The transmitter is enabled when set. When clear, no transmissions are allowed. When a frame is being transmitted, and STxON is cleared, then that transmit frame is completed.
The following procedure will correctly set the SelfCtl register value: 1. Read the value of SelfCtl 9 2. Clear PSPRS bit in SelfCtl Register. 3. Read/write PHY registers. 4. Restore the old value to SelfCtl. RWP: Remote Wake Pin. This bit reflects the current state of the REMWAKE pin. Following a system power up, caused by a Remote Wake-up frame being detected by the MAC, this bit is set. GPO0: General Purpose Output 0. This bit directly controls the GPO[0] pin.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RESET: Soft Reset. This is an act-once bit. When set, a Soft Reset is initiated immediately, this will reset the FIFO, mac and Descriptor Processor. This bit is cleared as a result of the reset. Driver software should wait until the bit is cleared before proceeding with MAC initialization.
DiagDa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DATA 15 14 13 12 11 10 9 8 DATA Address: 0x8001_003C - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Diagnostic Data Register. The Diagnostic Data Register provides access to the internal register pointed to by the value in the Diagnostic Address register. For debug only. Bit Descriptions: DATA: Internal register data value.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Bit Descriptions: 9 GTC: General Timer Count, read only. The timer count contains the running value of the timer function, it cannot be written to directly. When the General Timer Period is written and the same value is loaded into the General Timer Count, or when the count value reaches 0, it is reloaded from the General Timer Period. Additionally when the count reaches zero, the Timeout Status (Interrupt Status register) is set.
FCF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 MACCT 15 14 13 12 11 10 9 8 TPT Address: 0x8001_0048 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Flow Control Format Register Bit Descriptions: MACCT: MAC Control Type. The MAC Control Type field defines the Ethernet type field for receive and transmit MAC control frames.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 5. Pause time = Transmit Pause Time (FCF) (2bytes) 6. Padding to complete minimum size packet. 9 7. CRC AFP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD AFP Address: 0x8001_004C - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Address Filter Pointer Register Bit Descriptions: RSVD: Reserved. Unknown During Read.
IndAd 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 IAD 31 30 29 28 27 26 25 24 IAD 15 14 13 12 11 10 9 8 IAD Address: 0x8001_0050 through 0x8001_0055 - 6 Bytes - Read/Write, when AFP = 000b, 010b or 001b Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Individual Address Register.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide HashTbl 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 39 38 37 36 35 34 33 32 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 HTb 47 46 45 44 43 42 41 40 HTb 31 30 29 28 27 26 25 24 HTb 15 14 13 12 11 10 9 8 HTb Address: 0x8001_0050 through 0x8001_0057 - 8 Bytes - Read/Write, when AFP = 111b Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Hash Table Register.
TXCollCnt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 TXC Address: 0x8001_0070 - Read Only Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Transmit Collision Count Register Bit Descriptions: RSVD: Reserved. Unknown During Read. TXC: Transmit Collision Count. The transmit collision count records the total number of collisions experienced on the transmit interface, including late collisions.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Definition: Receive Miss Count Register 9 Bit Descriptions: RSVD: Reserved. Unknown During Read. RMC: Receive Miss Count. The Receive Miss Count records the number of frames that pass the destination address filter, but fail to be received due to lack of bus availability or lack of receive storage. Frames that are partially stored and marked as overruns are included in the count.
TestCtl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 MACF MFDX DB RSVD 15 14 13 12 11 10 9 8 RSVD RSVD Address: 0x8001_0008 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Test Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. MACF: MAC Fast. When set, internal MAC timers for link pulses and collision backoff are scaled in order to speed-up controller testing. When clear, normal timing is used.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Address: 0x8001_0024 - Read/Write 9 Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Interrupt Enable Register Bit Descriptions: RSVD: Reserved. Unknown During Read. RWIE: Remote Wake-up Interrupt Enable. Setting this bit causes an interrupt to be generated when a remote wake-up frame is detected and the MAC is in the Remote Wake-up mode (RXCtl). RxMIE: Receiver Miss Interrupt Enable.
MOIE: Receive Miss Overflow Interrupt Enable. If received frames are lost due to slow movement of receive data out of the receive buffers, then a receive miss is said to have occurred. When this happens, the RxMISS counter is incremented. When the MSB of the count is set, the MissCnt bit in the Interrupt Status Register is set. If the MissCntiE bit is set at this time, an interrupt is generated. TxCOIE: Transmit Collision Overflow Interrupt Enable.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide IntStsP/IntStsC 31 30 29 28 27 26 25 24 RSVD RWI RxMI RxBI RxSQI TxLEI ECI TxUHI 15 14 13 12 11 10 9 8 MIII PHYSI TI AHBE SWI RSVD 23 22 21 20 19 RSVD 7 6 RSVD 5 18 17 16 MOI TxCOI RxROI 1 0 4 3 2 OTHER TxSQ RxSQ RSVD Address: 0x8001_0028, for IntStsP - Read/Write 0x8001_002C, for IntStsC - Read Only Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Interrupt Status Preserve a
RxMI: RxMI is set when a receive frame was discarded due to the internal FIFO being full. This may be as a result of a long latency in acquiring the bus or a lack of receive descriptors. RxMiss is not set in response to a frame that was partially stored in the FIFO and then discarded due to lack of FIFO space. This is marked as an Overrun Error in the Status Queue. RxBI: RxBuffers is set when the last available receive descriptor has been read into the MAC (RxDesEnq = 0).
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RxROI: When a runt frame is received with a CRC error, the RxRuntCnt register is incremented, when the MSB of the count is set, the RuntOv bit is set in the Interrupt Status Register. If the RxROIE bit is set, an interrupt will be generated. MIIII: The MII Status bit is set whenever a management operation on the MII bus is completed. PHYI: The PHY Status bit is set when the MAC detects a change of status event in the PHY.
Global Interrupt Status Register 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RSVD: Reserved. Unknown During Read. 9 INT: Global interrupt bit. This bit is set whenever the MACint signal to the interrupt controller is active. Writing a one to this bit location will clear this bit until a new interrupt condition occurs.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide GlIntROSts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 INT RSVD Address: 0x8001_0068 - Read Only Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: General Interrupt Read-Only Status register. This is a read-only version of the Global Interrupt Status Register. Bit Descriptions: RSVD: Reserved. Unknown During Read.
Bit Descriptions: RSVD: Reserved. Unknown During Read. INT: Global interrupt force bit, write only, always reads zero. Writing a one to this bit will set the Global Interrupt Status bit, if it is enabled. Writing a zero has no effect. MII/PHY Access Register Descriptions All PHY registers are accessed through the MII Command, Data and Status Registers.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide 9 PHYAD: PHY Address. This field defines which external PHY is to be accessed. REGAD: Register Address. This field defines the particular register in the PHY to be accessed.
0x0000_0000 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide MII Status Register 9 Soft Reset: Definition: Bit Descriptions: RSVD: Reserved. Unknown During Read. Busy: MII Busy. The Busy bit is set whenever a command is written to the MII Command Register. It is cleared when the operation has been completed. Descriptor Processor Registers The Descriptor Processor Registers are in three parts: the bus master control, receive registers, and transmit registers.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide MT: Manual Transfer. Writing a one to this bit causes all internal FIFOs to be marked pending for transfer, as if they had crossed their threshold. This provides a mechanism for flushing stale status from the internal FIFOs, when the Timed Transfer is not used and non zero thresholds have been set.
TxEn: Transmit Enable. Writing a one to Transmit Enable causes transmit DMA transfers to be enabled. This is reflected in TxAct (Bus Master Status) being set. TxEn is an act-oncebit and will clear automatically when the enable is complete. The first time the TxEn bit is set following an AHB reset, or a TxChRes, the MAC performs a transmit channel initialization. During this initialization the TXDEnq is cleared, and the Transmit Descriptor and Status Queues are calculated.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RxEn: Receive Enable. Writing a one to Receive Enable causes receive DMA transfers to be enabled. This is reflected in RxAct (Bus Master Status) being set. This bit is an actonce-bit and will clear automatically when the enable is complete. The first time the RxEn bit is set following a AHB reset, or a RxChRes, the MAC performs a receive channel initialization.
RxAct: Receive Active. When this bit is set, the channel is active and may be in the process of transferring receive data. Following a RxDisable Command (Bus Master Control), when transfers have been halted, this bit is cleared. QID: Queue ID. The queue ID reflects the current or last DMA queue active on the AHB bus. When an AHB error halts DMA operation, this field may be used to determine the queue that caused the error.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RXDQBLen 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RDBL Address: 0x8001_0094 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Receive Descriptor Queue Base Length register.
Definition: Receive Descriptor Queue Current Length register. The Receive Descriptor Queue Current Length defines the number of bytes between the Receive Descriptor Current Address and the end of the receive descriptor queue. This value is used internally to wrap the pointer back to the start of the queue. The register should not normally be written. Bit Descriptions: RSVD: Reserved. Unknown During Read. RDCL: Receive Descriptor Current Length.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RXDEnq 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RDV 15 14 13 12 11 10 9 8 RSVD RDI Address: 0x8001_009C - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Receive Descriptor Enqueue register. The Receive Descriptor Enqueue register is used to define the number of valid entries in the descriptor queue.
0x0000_0000 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Unchanged 9 Chip Reset: Soft Reset: Definition: Receive Buffer Current Address register. The Receive buffer current address contains the current address being used to transfer receive data. This value may be useful in debugging. Bit Descriptions: RBCA: Receive Buffer Current Address.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RXStsQBLen 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSQBL Address: 0x8001_00A4 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Receive Status Queue Base Length. The Receive Status Queue Base Length defines the actual number of bytes in the receive status queue.
Definition: Receive Status Queue Current Length. The Receive Status Queue Current Length defines the number of bytes between the Receive Status Current Address and the end of the receive status queue. This value is used internally to wrap the pointer back to the start of the queue. The register should not normally be written to. Bit Descriptions: RSVD: Reserved. Unknown During Read. RSQCL: Receive Status Queue Current Length.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RXStsEnq 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSV 15 14 13 12 11 10 9 8 RSVD RSI Address: 0x8001_00AC - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Receive Status Enqueue register. The Receive Status Enqueue register is used to define the number of free entries available in the status queue.
0x0000_0000 99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Unchanged 9 Chip Reset: Soft Reset: Definition: Receive Header Length register. The Receive Header Length registers are used to generate status after receiving a specific portion of a receive frame. When the number of bytes specified in either register has been transferred to the external data buffer, an appropriate status is generated.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide Bit Descriptions: TDBA: Transmit Descriptor Base Address. TXDQBLen 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 TDBL Address: 0x8001_00B4 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Transmit Descriptor Queue Base Length register.
Soft Reset: Unchanged Definition: Transmit Descriptor Queue Current Length register. The Transmit Descriptor Queue Current Length defines the number of bytes between the Transmit Descriptor Current Address and the end of the transmit descriptor queue. This value is used internally to wrap the pointer back to the start of the queue. The register should not normally be written. Bit Descriptions: RSVD: Reserved. Unknown During Read. TDCL: Transmit Descriptor Current Length.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide TXDEnq 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 TDV 15 14 13 12 11 10 9 8 RSVD TDI Address: 0x8001_00BC - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Transmit Descriptor Enqueue register. The Transmit Descriptor Enqueue register is used to define the number of valid descriptors available in the transmit descriptor queue.
0x0000_0000 Soft Reset: 9 Unchanged Definition: Transmit Status Queue Base Address. The Transmit Status Queue Base Address defines the system memory address of the transmit status queue. This address is used by the MAC to reload the Transmit Current Status Address whenever the end of the status queue is reached. The base address should be set at initialization time and must be set to a word aligned memory address. Bit Descriptions: TSQBA: Transmit Status Queue Base Address.
99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide TXStsQCurLen 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 TSQCL Address: 0x8001_00C6 - Read/Write. Note half word alignment. Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Transmit Status Queue Current Length.
Definition: Transmit Status Queue Current Address. The Transmit Status Queue Current Address contains the address being used to transfer transmit status to the queue. This register is available for debugging. Bit Descriptions: TSQCA: Transmit Status Queue Current Address.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RDST: Receive Data Soft Threshold. The hard and soft threshold work in exactly the same manner except one. The soft threshold will not cause a bus request to be made if the bus is currently in use, but only when it is deemed to be idle (no transfers for four AHB clocks). The hard threshold takes effect immediately, regardless of the state of the bus.
TDST: Transmit Data Soft Threshold. The hard and soft threshold work in exactly the same manner except one. The soft threshold will not cause a bus request to be made if the bus is currently in use, but only when it is deemed to be idle (no transfers for four AHB clocks). The hard threshold takes effect immediately regardless of the state of the bus.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide The hard and soft threshold work in exactly the same manner except one. The soft threshold will not cause a bus request to be made if the bus is currently in use, but only when it is deemed to be idle (no transfers for four AHB clocks). The hard threshold takes effect immediately regardless of the state of the bus.
The hard and soft threshold work in exactly the same manner except one. The soft threshold will not cause a bus request to be made if the bus is currently in use, but only when it is deemed to be idle (no transfers for four AHB clocks). The hard threshold takes effect immediately regardless of the state of the bus.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RDST: Receive Descriptor Soft Threshold. 9 The hard and soft threshold work in exactly the same manner except one. The soft threshold will not cause a bus request to be made if the bus is currently in use, but only when it is deemed to be idle (no transfers for four AHB clocks). The hard threshold takes effect immediately regardless of the state of the bus.
TDST: Transmit Descriptor Soft Threshold. The hard and soft threshold work in exactly the same manner except one. The soft threshold will not cause a bus request to be made if the bus is currently in use, but only when it is deemed to be idle (no transfers for four AHB clocks). The hard threshold takes effect immediately regardless of the state of the bus.
99 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide TST: 9 Transmit Start Threshold. The transmit start threshold defines the number of bytes that must be written to the transmit data FIFO before a frame will start transmission on the serial interface. This value is primarily of concern when the transmit frame is spread across multiple descriptors and the first descriptors define small amounts of data.
10DMA Controller 10.1 Introduction The DMA Controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels that consist of 5 Memory to Internal Peripheral (M2P) transmit channels and 5 Peripheral to Memory (P2M) receive channels.
1010 DMA Controller EP93xx User’s Guide • Five hardware requests for M2M transfers; 2 for external peripherals that follow the handshake protocol, and 3 simple requests from IDE, SSPRx and SSPTx. • Independent source and destination address registers. Source and destination can be programmed to auto-increment or not for Memory-to-Memory channels. • Two buffer descriptors per M2P/P2M and M2M channel to avoid potential data underflow/overflow due to software introduced latency.
The DMA controller memory-to-memory channels can also be used in “Memory to External Peripheral” mode with handshaking protocol. A set of external handshake signals DREQ, DACK and TC/DEOT are provided for each of 2 M2M channels. • DREQ (input) can be programmed edge or level active, and active high or low. The peripheral may hold DREQ active for the duration of the block transfers or may assert/deassert on each transfer. • DACK (output) can be programmed active high or low.
1010 DMA Controller EP93xx User’s Guide The transaction is initiated by a SSP or IDE request.This request is masked after each peripheral width transfer, in order to allow latency for the peripheral to deassert its request line.The transfer terminates when the Byte Count Register equals zero. • Memory and External Bus. These can be memory- or FIFO-based and memory-mapped through the SMC.
occurred. If the ICE bit is not set, then the DMA flushes the last good data out to memory and terminates the transfer for the current buffer. Where whole words are present in the packer, word transfers are used. For the remaining bytes (up to a maximum of 3), byte transfers are used. Thus the maximum number of bus transfers performed to empty the packer is 6, that is, 3 word transfers and 3 byte transfers.
1010 10 DMA Controller EP93xx User’s Guide 10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and for External Peripherals without Handshaking Signals When a M2M channel is set up to transfer to/from SSP, IDE or an external peripheral, the transfer width used (that is, the AMBA HSIZE signal) is determined by the peripheral width programmed via the CONTROL.PW bits of the channel.
The data received on each of the five peripheral receive DMA Rx Data buses is transferred into an internal receive packer unit. The packer unit is used to convert the byte-wide data received from the peripheral into words to be transferred over the system bus to the memory. The packer unit stores 4 words (one quad-word) of data, which is the size of the burst transfers to and from memory over the system bus. Provision for the memory access latency is provided by FIFOs within the peripheral.
1010 10 DMA Controller EP93xx User’s Guide CE: Channel (Peripheral) Error ICE: CONTROL[6] - Ignore Channel Error. This bit may be set for data streams whereby the end user can tolerate occasional bit errors. If it is not set then the DMA will abort its transfer in receipt of a peripheral error. ABORT: CONTROL[5] 10.1.9.1.1 DMA_IDLE The DMA Channel FSM always resets to the DMA_IDLE state. The DMA Channel FSM always enters the DMA_IDLE state when the channel is disabled (CONTROL[4]). 10.1.9.1.
10.1.9.2 Data Transfer Initiation and Termination The DMA Controller initiates data transfer in the receive direction when: • A packer unit becomes full • A packer unit, dependent on the next address access, contains enough data for an unaligned byte/word access. The DMA Controller stops data transfers in the receive direction and moves onto the next buffer when: • RxEnd signal is asserted to indicate end of received data or received error.
1010 DMA Controller EP93xx User’s Guide 10.1.10 M2M DMA Functional Description 10.1.10.1 M2M DMA Control Finite State Machine Each DMA M2M channel is controlled by 2 finite state machines (FSM) which determine whether the channel is transferring data to or from memory, which buffer from the doublebuffer descriptor set it is using, and whether it is currently generating an interrupt.
No data transfers occur in this state. 10.1.10.1.3 DMA_MEM_RD The DMA M2M Control FSM enters the DMA_MEM_RD state when a M2M channel has received a software trigger to begin a transfer, that is, the START bit is set (CONTROL[4]) and CONTROL.TM = “00”; or when IDE or SSP asserts its request line and CONTROL.TM = “01” or “10”; or when an external device asserts its DREQ o/p to the DMA and CONTROL.TM = “01” or “10”.
1010 DMA Controller EP93xx User’s Guide 10.1.10.1.5 DMA_BWC_WAIT The DMA M2M Control FSM enters the DMA_BWC_WAIT state when the byte count is within 15 bytes of a multiple of the BWC value. The DMA M2M Control FSM stays in this state for one cycle only. 10.1.10.2 M2M Buffer Control Finite State Machine 10 DMA_NO_BUF BCRx_WRITE (x = 0 or 1) Buffer End Buffer End DMA_BUF_NEXT DMA_BUF_ON BCRx_WRITE(x = 1 or 0) Figure 10-3. M2M DMA Buffer Finite State Machine 10.1.10.2.
(which BCRx is free can be determined using the STATUS.Nextbuffer status bit - see “STATUS” on page 10-37). When the DMA Buffer FSM transitions from DMA_BUF_ON to DMA_NO_BUF state due to end of buffer, the DONE status bit is asserted and the DONE interrupt is set if enabled. The TC (Terminal Count) output is asserted by the DMA to the external device if the BCR register has expired for the current buffer (when in external DMA transfer mode and TC is programmed as an output signal from the DMA).
1010 DMA Controller EP93xx User’s Guide The DMA Controller initiates memory-to-memory transfers in the receive direction (that is, from memory/peripheral to DMA) under the following circumstances: • A channel has been triggered by software, that is, setting the START bit to “1”. Setting the START bit causes the channel to begin requesting the bus, and when granted ownership it will start transferring data immediately. The DMA controller drives the SAR_BASEx value onto the internal AHB address bus.
• For a software-triggered M2M transfer, a memory-write is initiated when the 16-byte data bay has been filled (in the case where 16 or more bytes remain to be transferred) or when it contains the appropriate number of bytes (equal to BCR register value if BCR is less than 16). The DMA controller drives the DAR_BASEx onto the address bus. This address can be any aligned byte address. The BCR register decrements by the appropriate number of bytes. When BCR = 0 then the transfer is complete.
1010 10 DMA Controller EP93xx User’s Guide When the DONE interrupt is set, the processor can then write a one to clear the interrupt before reprogramming the DMA to carry out another external DMA transfer. If the DEOT_TC pin is configured as an output pin (TC), the DMA asserts TC when each buffers byte count expires. It then rolls over to the other buffer.
Subsequent changes on DREQ are ignored until the pending request begins to be serviced. When the pending request has begun to be serviced, the DREQS status bit is cleared and subsequent edge-triggered requests are again recognized (latched) by the DMA. The DREQS status bit can be cleared by a software write to the channel STATUS register, thus causing the DMA to ignore the request.
1010 DMA Controller EP93xx User’s Guide At the start of a receive or transmit data transfer, the AHB Master Interface uses the low order 4 bits of the current DMA address to decide on the data transfer size to use. If the low-order 4 bits are zero, the first transfer is a quad word access. If they are not all zero, then if the loworder two bits are zero, then the first transfer is a word transfer.
10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors Only one Rx buffer descriptor is allocated per transaction. There are five Rx buffer descriptors, one for each of the five receive channels. Each buffer descriptor allows a channel double buffering scheme by containing programming for two buffers, that is, two system buffer base addresses and two buffer byte counts.
1010 DMA Controller EP93xx User’s Guide Table 10-2. M2P DMA Bus Arbitration (Continued) Internal Arbitration Priority 10 Lowest CHARB = 0 CHARB = 1 M2P Ch 7 M2P Ch 8 M2P Ch 9 M2M Ch 0 M2M Ch 1 M2P Ch 5 M2P Ch 6 M2P Ch 7 M2P Ch 8 M2P Ch 9 During normal operation, using the “fair” rotating priority scheme shown in Table 10-2, the last channel to be serviced becomes the lowest priority channel with the others rotating accordingly.
Table 10-3. DMA Memory Map ARM920T Address Description Channel Base Address 0x8000_0340 -> 0x8000_037C M2P Channel 8 Registers (Tx) DMA Channel Arbitration register DMA Global Interrupt register Not Used 0x8000_0340 0x8000_0380 0x8000_03C0 0x8000_03C4 -> 0x8000_FFFC 0x8000_03C4 10 10.2.
1010 10 DMA Controller EP93xx User’s Guide Register Descriptions CONTROL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ICE ABORT ENABLE ChErrorIntEn RSVD NFBIntEn STALLIntEn RSVD 15 14 13 12 11 10 RSVD 9 8 7 Address: Channel Base Address + 0x0000 - Read/Write Definition: This is the Channel Control Register, used to configure the DMA Channel. Important Programming Note: The control register should be read immediately after being written.
ABORT: This bit determines how the DMA Channel State machine behaves while in the NEXT state and in receipt of a peripheral error, indicated on RxEnd/TxEnd. This bit is ignored when ICE is set. 0 - NEXT -> ON state, effectively ignoring the error. 1 - NEXT -> STALL state, effectively disabling the channel. No STALLInt interrupt is set for this condition. ICE: Ignore Channel Error bit.
1010 DMA Controller EP93xx User’s Guide NOTE: The naming convention used for channels and ports is as follows - even numbers correspond to transmit channels/ports and odd numbers correspond to receive channels/ports. Table 10-5.
INTERRUPT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ChErrorInt 0 NFBInt STALLInt RSVD 15 14 13 12 11 10 9 8 7 RSVD Address: Channel Base Address + 0x0004 - Read/Write Definition: This is the interrupt status register. The register is read to obtain interrupt status for enabled interrupts. An interrupt is enabled by writing the corresponding bits in the CONTROL register. Write this location once to clear the interrupt.
1010 DMA Controller EP93xx User’s Guide STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ChError RSVD NFB STALL RSVD 15 14 10 13 12 11 RSVD 10 9 8 BYTES 7 NextBuffer Current State Address: Channel Base Address + 0x000C - Read Only Definition: This is the channel status register, which is a read-only register, used to provide status information with respect to the DMA channel. Bit Descriptions: RSVD: Reserved. Unknown During Read.
Current State: Indicates the state that the Channel FSM is currently in: 00 - IDLE 01 - STALL 10 - ON 11 - NEXT NextBuffer: Informs the NFB service routine, after a NFB interrupt, which pair of BASEx/MAXCOUNTx registers is free for update. 0 - Update MAXCNT0/BASE0 1 - Update MAXCNT1/BASE1 The NextBuffer bit gets set to “1” when a write occurs to BASE0 and it gets set to “0” when a write occurs to BASE1. This bit alone cannot be used to determine which of the two buffers is currently being transferred to.
1010 DMA Controller EP93xx User’s Guide REMAIN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 10 9 8 REMAIN Address: Channel Base Address + 0x0014 - Read Only Definition: The Channel Bytes Remaining Register contains the number of bytes remaining in the current DMA transfer. Only the lower 16 bits are valid Bit Descriptions: RSVD: Reserved. Unknown During Read.
MAXCNTx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 10 MAXCNTx Address: MAXCNT0: Channel Base Address + 0x0020 - Read/Write MAXCNT1: Channel Base Address + 0x0030 - Read/Write Definition: x = “0” or “1”. Maximum byte count for the buffer. Represents the double buffer per channel. Only the low order 16 bits are used. Each MAXCNTx register must be programmed before it’s corresponding BASEx register.
1010 DMA Controller EP93xx User’s Guide CURRENTx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CURRENTx 15 14 13 12 11 10 9 10 8 7 CURRENTx Address: CURRENT0: Channel Base Address + 0x0028 - Read Only CURRENT1: Channel Base Address + 0x0038 - Read Only Definition: This is the Channel Current Address Register. Bit Descriptions: CURRENTx: Returns the current value of the channel address pointer.
Table 10-8.
1010 DMA Controller EP93xx User’s Guide of the source and destination addresses to avoid any problems in the case where software erroneously programs a byte-aligned address. The SCT bit is used only when in M2M software-triggered transfer mode. 10 DoneIntEn: Setting this bit to “1” enables the generation of the DONE Interrupt which indicates if the transfer completed successfully. ENABLE: Setting this bit to 1 enables the channel, clearing this bit disables the channel.
Example: if BWC = 1010b (indicating 1024 bytes, see Table 10-9, below), the DMA relinquishes control of the bus on completion of the current burst transfer after BCR values which are within 15 bytes of multiples of 1024. Table 10-9. BWC Decode Values PW: BWC Bytes 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Full DMA transfer completes 16 16 16 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 10 Peripheral Width.
1010 DMA Controller EP93xx User’s Guide 10 DAH: Destination Address Hold - This bit is used for external M2P transfers where the external memory destination is a memory-mapped FIFO-based device (with one address location) or for internal peripheral transfers (M2P) to the peripheral’s FIFO buffer. 1 - Hold the destination address throughout the transfer (do not increment). 0 - Increment the destination address after each transfer in the transaction.
NFBIntEn: Setting this bit to “1” enables the generation of the NFB interrupt in the DMA_BUF_ON state of the DMA channel buffer state machine. Setting this bit to zero disables generation of the NFB Interrupt. Normally when the channel is enabled, this bit should be 1. However in the case where the current buffer is the last, then this bit can be cleared to prevent the generation of an interrupt while the DMA State machine is in the DMA_BUF_ON state. RSS: Request Source Selection. 00 - External DReq.
1010 10 DMA Controller EP93xx User’s Guide Definition: This is the interrupt status register. The register is read to obtain interrupt status for enabled interrupts. An interrupt is enabled by writing the corresponding bits in the CONTROL register. Write this location once to clear the interrupt. (See the Interrupt Register Bit Descriptions for the bits where this applies.) Bit Descriptions: RSVD: Reserved. Unknown During Read. STALLInt: Indicates channel has stalled.
STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 RSVD 13 12 11 DREQS NB NFB 10 9 EOTS 8 TCS DONE CurrentState STALL Address: Channel Base Address + 0x000C - Read/Write Definition: This is the channel status register, used to provide status information with respect to the DMA channel. All register bits are read-only except for the DREQS status bit which can be cleared by a write (either a “0” or a “1”) to this register.
1010 DMA Controller EP93xx User’s Guide CurrentState: Indicates the states that the M2M Channel Control FSM and M2M Buffer FSM are currently in: CurrentState[2:0] - These indicate the state of M2M Channel Control FSM: 000 - DMA_IDLE 001 - DMA_STALL 010 - DMA_MEM_RD 011 - DMA_MEM_WR 100 - DMA_BWC_WAIT 10 CurrentState[4:3] - These indicate the state of M2M Buffer FSM: 00 - DMA_NO_BUF 01 - DMA_BUF_ON 10 - DMA_BUF_NEXT DONE: Transfer completed successfully.
EOTS: End-Of-Transfer status (valid only if the DEOT/TC pin has been programmed for the DEOT function, that is, the control reg bit ETDP[1] = 0) for buffer descriptor 1 or 0 respectively. 00 - End of transfer has not been requested by external device for either buffer descriptor. 01 - End of transfer has been requested by external device for buffer descriptor 0 only. 10 - End of transfer has been requested by external device for buffer descriptor 1 only.
1010 DMA Controller EP93xx User’s Guide The NextBuffer status bit can be used in conjunction with the CurrentState status bits to determine the active buffer according to the following rules: If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 1 then Buffer0 is the active buffer. If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 0 then Buffer1 is the active buffer. 10 If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer = 0 then Buffer0 is the active buffer.
to indicate that the external device has requested service. The STATUS register is written by software to clear the DREQS status bit, thus causing the DMA to ignore the request. For level-sensitive DREQ mode, do not attempt to clear the DREQS status bit, as the request will keep coming from the external device. The hardware ensures that a write to the STATUS register has no effect when in levelsensitive mode.
1010 DMA Controller EP93xx User’s Guide For a double/multiple buffer transfer, the second buffer descriptor can be programmed while the transfer using the first buffer is being carried out (thus reducing software latency impact). The NFB interrupt is generated when transfer begins using the second buffer. The NFB interrupt service routine can then be used to update the free buffer descriptor (in the case where a third buffer is required).
DAR_BASEx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DAR_BASEx 15 14 13 12 11 10 9 8 7 10 DAR_BASEx Address: DAR_BASE0: Channel Base Address + 0x002C- Read/Write DAR_BASE1: Channel Base Address + 0x0030 - Read/Write Definition: This register contains the base memory address to which the DMA controller transfers data. Bit Descriptions: DAR_BASEx: x = 0 or 1 representing the double buffer per channel.
1010 DMA Controller EP93xx User’s Guide Bit Descriptions: SAR_CURRENTx: Returns the current value of the channel source address pointer. Upon writing the BCRx register, the contents of the SAR_BASEx register is loaded into the SAR_CURRENTx register and the x buffer becomes active. Following completion of a transfer from a buffer, the postincremented address is stored in this register so that a software service routine can detect the point in the buffer at which transfer was terminated.
Address: 0x8000_03C0 - Read/Write Definition: DMA Global Interrupt Register. This register indicates which channels have an active interrupt. It is a read only register. Bit Descriptions: RSVD: Reserved. Unknown During Read. D0 - D1: These interrupts are per channel interrupts, as shown in Table 10-10. Each bit is a logical OR of the INTERRUPT register per channel. There are no dedicated storage of these channel interrupts.
1010 DMA Controller EP93xx User’s Guide Definition: DMA Channel Arbitration Register. This bit controls the DMA channel arbitration. Bit Descriptions: 10 RSVD: Reserved. Unknown During Read. CHARB: This bit controls DMA channel arbitration. It is reset to “0”, thus giving a default setting of internal Memory-toPeripheral channels having a higher priority than Memoryto-Memory channels.
11Universal Serial Bus Host Controller 1111 Chapter 11 11 11.1 Introduction Note: The EP9301 and EP9302 processors each have 2 USB 2.0 Host ports. Note: The EP9307, EP9312, and EP9315 processors each have 3 USB 2.0 Host ports. The Universal Serial Bus (USB) Host Controller enables communication to USB 2.0 lowspeed (1.2 Mbps) and full-speed (12 Mbps) devices. The controller supports three root hub ports and complies with the Open Host Controller Interface (OpenHCI) specification, version 1.0a.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide The Client Software/USB Device and Host Controller Driver are implemented in software. The Host Controller and USB Device are implemented in hardware. OpenHCI specifies the interface between the Host Controller Driver and the Host Controller and describes the fundamental operation of each. Client Software USB Driver Software 11 Host Controller Driver Scope of OpenHCI Host Controller Hardware USB Device Figure 11-1.
11.2.2 Host Controller Interface 11.2.2.1 Communication Channels There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the HC. The Host Controller is the target for all communication on this channel. The operational registers contain control, status, and list pointer registers.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11.2.2.2 Data Structures The basic building blocks for communication across the interface are the Endpoint Descriptor (ED) and Transfer Descriptor (TD). The Host Controller Driver assigns an Endpoint Descriptor to each endpoint in the system. The Endpoint Descriptor contains the information necessary for the Host Controller to communicate with the endpoint.
scheduling the Endpoint Descriptor at the appropriate depth in the tree. The higher the polling rate, the closer to the root of the tree the Endpoint Descriptor will be placed since multiple lists will converge on it. Figure 11-4 illustrates the structure for Interrupt Endpoints. The Interrupt Endpoint Descriptor Placeholder indicates where zero or more Endpoint Descriptors may be enqueued. The numbers on the left are the index into the HCCA interrupt head pointer array.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide Interrupt Endpoint Descriptors 11 Interrupt Head Pointers 0 16 8 24 4 20 12 28 2 18 10 26 6 22 14 30 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 32 16 8 4 2 1 Endpoint Poll Interval (ms) Figure 11-5. Sample Interrupt Endpoint Schedule 11.2.3 Host Controller Driver Responsibilities This section summarizes the Host Controller Driver (HCD) responsibilities. 11.2.3.
A portion of the bandwidth is reserved for nonperiodic transfers. This ensures that some amount of bulk and control transfers will occur in each frame period. The frame period is defined for USB to be 1.0 ms. The bandwidth allocation policy for OpenHCI is shown in Table 11-1. Each frame begins with the Host Controller sending the Start of Frame (SOF) synchronization packet to the USB bus.
1111 11 Universal Serial Bus Host Controller EP93xx User’s Guide 11.2.4 Host Controller Responsibilities This section summarizes the Host Controller (HC) responsibilities. 11.2.4.1 USB States There are four USB states defined in OpenHCI: UsbOperational, UsbReset, UsbSuspend, and UsbResume. The Host Controller puts the USB bus in the proper operating mode for each state. 11.2.4.2 Frame Management The Host Controller keeps track of the current frame counter and the frame period.
Data Control AHB Slave Addr USB State Control Control Root Hub & Host SIE HCI Slave A Control H B Cntrl USB Host Test Reg H C I Data Data Data FIFO 64x8 Data P L L XVR 2 USB XVR 3 USB Status HCI Master Cntrl USB Control B U Addr/ Data S AHB Master XVR 1 ED/TD Data ED/TD Status List Processor (including End Descriptor and Transfer Descriptor registers) Control Figure 11-6. USB Host Controller Block Diagram 11.2.5 USB Host Controller Blocks 11.2.5.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11.2.5.4 HCI Master Block The HCI Master Block handles read/write requests to system memory that are initiated by the List Processor while the Host Controller (HC) is in the operational state and is processing the lists queued in by HCD. It generates the addresses for all the memory accesses, which is the DMA functionality.
11.3 Registers The Host Controller (HC) contains a set of on-chip operational registers that are used by the Host Controller Driver (HCD). According to the function of these registers, they are divided into four partitions, specifically for Control and Status, Memory Pointer, Frame Counter and Root Hub. All of the registers should be read and written as Dwords. The memory map is shown in Table 11-2. 11 Table 11-2.
1111 11 Universal Serial Bus Host Controller EP93xx User’s Guide OpenHCI Implementation Specific Registers The Root Hub partition contains registers that have power-on reset values that are implementation specific. The values for the processor are indicated in the Default field for each register, below.
Definition: Controls the host controller’s operating modes. Bit Descriptions: RSVD: Reserved. Unknown During Read. CBSR: ControlBulkServiceRatio: This specifies the service ratio between Control and Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11 BLE: BulkListEnable: This bit is set to enable the processing of the Bulk list in the next Frame. If cleared by HCD, processing of the Bulk list does not occur after the next SOF. HC checks this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list.
RWE: RemoteWakeupEnable: This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling. When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide CLF: ControlListFilled: This bit is used to indicate whether there are any TDs on the Control list. It is set by HCD whenever it adds a TD to an ED in the Control list. When HC begins to process the head of the Control list, it checks CLF. As long as ControlListFilled is 0, HC will not start processing the Control list. If CF is 1, HC will start processing the Control list and will set ControlListFilled to 0.
HcInterruptStatus 31 30 RSVD OC 15 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RHSC FNO UE RD SF WDH SO RSVD 13 12 11 10 RSVD 9 8 7 Address: 0x8002_000C Default: 0x0000_0000 Definition: Provides interrupt status information. Bit Descriptions: RSVD: Reserved. Unknown During Read. SO: SchedulingOverrun. This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11 FNO: FrameNumberOverflow. This bit is set when the MSB of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. RHSC: RootHubStatusChange. This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. OC: OwnershipChange. This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
FNO: FrameNumberOverflow. Enable interrupt generation due to Frame Number Overflow. RHSC: RootHubStatusChange. Enable interrupt generation due to Root Hub Status Change. OC: OwnershipChange. Enable interrupt generation due to Ownership Change. MIE: Master Interrupt Enable. A zero written to this field is ignored by HC. A one written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as a Master Interrupt Enable.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11 FNO: FrameNumberOverflow: Disable interrupt generation due to Frame Number Overflow. RHSC: RootHubStatusChange: Disable interrupt generation due to Ownership Change. OC: OwnershipChange. Enable interrupt generation due to Ownership Change. MIE: Master Interrupt Enable: A zero written to this field is ignored by HC. A one written to this field disables interrupt generation due to events specified in the other bits of this register.
Default: 0x0000_0000 Definition: Physical address of the current isochronous or interrupt endpoint descriptor. Bit Description: RSVD: Reserved. Unknown During Read. AD: PeriodCurrentED. This is used by HC to point to the head of one of the Periodic lists which will be processed in the current Frame. The content of this register is updated by HC after a periodic ED has been processed. HCD may read the content in determining which ED is currently being processed at the time of reading.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide HcControlCurrentED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 AD 15 14 13 12 11 10 11 9 8 AD RSVD Address: 0x8002_0024 Default: 0x0000_0000 Definition: Physical address of the current endpoint descriptor of the control list. Bit Description: RSVD: Reserved. Unknown During Read. AD: ControlCurrentED. This pointer is advanced to the next ED after serving the present one.
Physical address of the first endpoint descriptor of the bulk list. Bit Description: RSVD: Reserved. Unknown During Read. AD: BulkHeadED. HC traverses the Bulk list starting with the HcBulkHeadED pointer. The content is loaded from HCCA during the initialization of HC.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide HcDoneHead 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 AD 15 14 13 12 11 10 11 9 8 AD RSVD Address: 0x8002_0030 Default: 0x0000_0000 Definition: Physical address of the last completed transfer descriptor that was added to the done list. Bit Description: RSVD: Reserved. Unknown During Read. AD: DoneHead.
RSVD: Reserved. Unknown During Read. FI: FrameInterval. This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11,999. HCD should store the current value of this field before resetting HC. By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value. HCD may choose to restore the stored value upon the completion of the Reset sequence. FSMPS: FSLargestDataPacket.
1111 11 Universal Serial Bus Host Controller EP93xx User’s Guide FRT: FrameRemainingToggle. This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD for the synchronization between FrameInterval and FrameRemaining.
0x8002_0040 Default: 0x0000_0000 Definition: Defines the earliest time the host controller should start processing the periodic list. 11 Bit Description: RSVD: Reserved. Unknown During Read. PS: PeriodicStart. After a hardware reset, this field is cleared. This is then set by HCD during the HC initialization. The value is calculated roughly as 10% off from HcFmInterval. A typical value will be 0x03E67.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide HcRhDescriptorA 31 30 29 28 27 26 25 24 23 22 21 20 P 15 14 11 RSVD 13 19 18 17 16 3 2 1 0 RSVD 12 11 10 9 8 NOCP OCPM DT NPS PSM 7 6 5 4 NDP Address: 0x8002_0048 Default: 0x0200_1203 Definition: Describes the root hub. Bit Descriptions: RSVD: Reserved. Unknown During Read. NDP: NumberDownstreamPorts. These bits specify the number of downstream ports supported by the Root Hub.
NPS: NoPowerSwitching. These bits are used to specify whether power switching is supported or port are always powered. It is implementation-specific. When this bit is cleared, the PowerSwitchingMode specifies global or perport switching. 0: Ports are power switched 1: Ports are always powered on when the HC is powered on. DT: DeviceType. This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read/write 0.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide Default: 0x0000_0000 Definition: Describes the root hub. Bit Descriptions 11 RSVD: Reserved. Unknown During Read. DR: DeviceRemovable. Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable.
RSVD: Reserved. Unknown During Read. LPS: (READ) LocalPowerStatus. The Root Hub does not support the local power status feature; thus, this bit is always read as “0”. (WRITE) ClearGlobalPower: In global power mode (PowerSwitchingMode=0), this bit is written to “1” to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a “0” has no effect. OCI: OverCurrentIndicator.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide HcRhPortStatusx 31 30 29 28 27 26 25 24 23 22 21 RSVD 15 14 11 13 12 11 10 RSVD 9 8 LSDA PPS 7 6 RSVD 5 20 19 18 17 16 PRSC OCIC PSSC PESC CSC 4 3 2 1 0 PRS POCI PSS PES CCS Address: HcRhPortStatus1 - 0x8002_0054, HcRhPortStatus2 - 0x8002_0058, HcRhPortStatus3 - 0x8002_005C Default: 0x0000_0100 Definition: Control/status for root hub port 1, 2, and 3 respectively Bit Descriptions: CCS: (READ)
PES: (READ) PortEnableStatus. This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. This change also causes PortEnabledStatusChange to be set. HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide POCI: 11 (READ) PortOverCurrentIndicator. This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0 = no overcurrent condition.
(WRITE) SetPortPower: The HCD writes a “1” to set the PortPowerStatus bit. Writing a “0” has no effect. Note: This bit is always reads “1” if power switching is not supported. LSDA: (READ) LowSpeedDeviceAttached. This bit indicates the speed of the device attached to this port. When set, a Low Speed device is attached to this port. When clear, a Full Speed device is attached to this port. This field is valid only when the CurrentConnectStatus is set.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11 OCIC: PortOverCurrentIndicatorChange. This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a “1” to clear this bit. Writing a “0” has no effect. 0 = no change in PortOverCurrentIndicator 1 = PortOverCurrentIndicator has changed PRSC: PortResetStatusChange. This bit is set at the end of the 10 ms port reset signal.
USBHCISts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RWU MSN MBA RSVD 15 14 13 12 11 10 9 8 RSVD Address: 0x8002_0084 - Read/Write Default: 0x0000_0000 Definition: Host Controller Interface. Some status bits reporting from USB host controller to software. Bit Descriptions: RSVD: Reserved. Unknown During Read. MBA: Host controller buffer access indication. When asserted, it indicates that currently host controller is accessing data buffer.
1111 Universal Serial Bus Host Controller EP93xx User’s Guide 11 11-38 DS785UM1 Copyright 2007 Cirrus Logic
12Static Memory Controller 1212 Chapter 12 12 12.1 Introduction Note: In the EP9301 and 9302 processors, the common address/data bus is 16-bits wide and the Static Memory Controller (SMC) supports 8-bit and 16-bit devices. Note: In the EP9307, EP9312, and EP9315 processors, the common address/data bus is programmable to either 16-bits or 32-bits wide, and the SMC supports 8-bit, 16-bit, and 32-bit devices. Note: PCMCIA (PC Card) is supported in the EP9315 processor only.
1212 Static Memory Controller EP93xx User’s Guide The SMC has five main functions: 1. Memory bank selecting 2. Access timing 3. Wait State generation 4. Byte lane write enabling 12 5. External bus interfacing 12.2 Static Memory Controller Operation The SMC provides access to static memory devices that are attached to the external bus. The SMC can work with a wide variety of external device types, including SRAM, ROM, NOR FLASH, and peripherals that respond to SRAM-type signaling.
AD[x] Data Read 1212 Static Memory Controller EP93xx User’s Guide 12 DA[x] nCSx RDn/OEn HCLK Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive AD[x] Data Write DA[x] nCSx WRn and nDMQ[3:0] HCLK Figure 12-2.
1212 Static Memory Controller EP93xx User’s Guide Address Data Read Data 12 nCSx RDn/OEn Delay due to WAITn synchronization WAITn HCLK Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Active AD[x] Data Write DA[x] nCSx WRn and nDMQ[1:0] Delay due to WAITn synchronization WAITn HCLK Figure 12-4.
If the bit-width of an internal device that generates a read or write request is larger than the bit-width of the memory device in the target memory space, the SMC will perform multiple successive read or write accesses to the external device. For example, if an internal device generates a 16-bit read request to an 8-bit external memory device, the SMC will perform two successive read accesses to the 8-bit external device.
1212 Static Memory Controller EP93xx User’s Guide Table 12-2. PCMCIA Pin Usage (Continued) Pin Name IOWRn MCREGn MCELn MCEHn MCRESETn MCWAIT AD[10:8] AD[7:0] DA[15:0] MCDIR MCDAENn MCADENn VS2 READY VS1 MCBVD2 MCBVD1 MCD2 MCD1 WP Not Implemented 12 Alternate Use If No Card GPIO.F[7] GPIO.F[6] GPIO.F[5] GPIO.F[4] GPIO.F[3] GPIO.F[2] GPIO.F[1] GPIO.
RUN GPIO PORT F[7:0] 12 nCF_MCBVD [2:1] nCF_VS [2:1] Status Buffer NCE_MCD [2:1] NCE_WP, NCE_READY DA[15:0] MCDAENn 1212 Static Memory Controller EP93xx User’s Guide Data Transceiver PC_D[15..0] PCMCIA Connector MCDIR Processor Pins AD[7:0] Address Buffer PC_A[7..0] MCADENn AD[25:8] PC_A[25:8] MCWRn nPWE MCRDn nPOE MCWAIT nWAIT MCEHn nPC_CE2 MCELn nPC_CE1 IORDn nPIORD IOWRn nPIOWR MCREGn nPREG MCRESETn RESET_1 READY PC_RDY Figure 12-5.
1212 Static Memory Controller EP93xx User’s Guide 12.4 PC Card Memory-Mode Enable Signals PC Card memory-mode enable signals, nPC_CE1 and nPC_CE2, are output on pin MCELn and pin MCEHn, respectively. Along with the address signal output on pin AD[0] and the data signals input or output on pins DA[15:8] and DA[7:0], the nPC_CE1 and nPC_CE2 signals specify the type of access that is being made to the particular segment of memory in the PC Card, as shown in Table 12-3 and Table 12-4. 12 Table 12-3.
Table 12-6.
1212 Static Memory Controller EP93xx User’s Guide 12.6 Registers Table 12-8.
Bit Descriptions: RSVD: Reserved - Unknown During Read IDCY: Idle Cycle - Read/Write The value written to this field specifies the memory data bus turnaround time between a Read access and a Write access. The turnaround time is specified by (IDCY + 1) HCLKs. For example, if IDCY = 0xA, the turnaround time is 10 + 1 = 11 cycles of HCLK.
1212 Static Memory Controller EP93xx User’s Guide The number of wait cycles for each of the 2nd, 3rd, and 4th accesses is specified by (WST2 + 1) HCLKs. For example, if WST2 = 0x4, 4 + 1 = 5 cycles of HCLK are inserted into the timing for each of the 2nd, 3rd, and 4th accesses. On reset, this field defaults to 0x1F (slowest access) to enable booting from ROM or FLASH memory device types.
EBIBRKDIS: EBI Break Disable - Read/Write The value written to this bit specifies the circumstances for when the SMC will release the external memory bus: 0 - The SMC releases the external memory bus at the end of each access to this memory bank 1 - The SMC releases the external memory bus after it has completed all pending accesses to this memory bank 12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only) The SMC has additional functionality to support a PC-card in Memory Bank 4.
1212 Static Memory Controller EP93xx User’s Guide The data strobe assertion time is specified by (AA+1) HCLK cycles. For example, if AA = 0x10, the data strobe assertion time is 16 + 1 = 17 cycles of HCLK HA: Attribute space Hold time - Read/Write The value written to this field specifies the minimum ‘number of HCLK cycles, minus 1’ between de-asserting the data strobe, MCDAENn, and de-asserting the address strobe, MCADENn. 12 The Hold time is specified by (HA +1) HCLK cycles.
The value written to this field specifies the minimum ‘number of HCLK cycles, minus 1’ that the data strobe, MCDAENn, is asserted during a Read or Write access. The data strobe assertion time is specified by (AC+1) HCLK cycles.
1212 Static Memory Controller EP93xx User’s Guide 0 - 8-bit wide Common space 1 - 16-bit wide Common space AI: IO Space Access time - Read/Write The value written to this field specifies the minimum ‘number of HCLK cycles, minus 1’ that the data strobe, MCDAENn, is asserted during a Read or Write access. 12 The data strobe assertion time is specified by (AI+1) HCLK cycles.
PCEN: PC Card Enable - Read/Write Writing a “1” to this bit enables the PC Card interface. PCRST: PC Card Reset - Read/Write Writing a ‘1’ to this bit clears the Configuration Option register in the card. This places the card into an unconfigured (memory only interface) state. 12 Writing a ‘0’ to this bit allows normal PC Card operation. WEN: External Wait Enable - Read/Write Writing a ‘1’ to this bit enables the MCWAIT input pin to be asserted by the card to insert wait cycles into the access timing.
1212 Static Memory Controller EP93xx User’s Guide 12 12-18 DS785UM1 Copyright 2007 Cirrus Logic
13SDRAM, SyncROM, and SyncFLASH Controller 1313 Chapter 13 13 13.1 Introduction Note: In the EP9301 and 9302 processors, the common address/data bus is 16-bits wide and the SDRAM, SyncROM, and SyncFLASH synchronous memory controller supports 16-bit and 8-bit devices.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide Length = 0x4 (32-bit wide memory bus) or Burst Length = 0x8 (16-bit wide memory bus) to the Mode register that is inside the SyncROM device.
it’s data outputs in the high impedance state. If power-on reset has become deasserted, the ARM Core is released from the reset state. 13.3 Address Pin Usage Each of the four synchronous memory domains can be fitted with a variety of device types, provided the total capacitance on any address/control/data line does not exceed the specified operating limit.
1313 13 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide the synchronous memory map. Refer to Table 13-11 to compare the memory space with SROMLL=1 and SROMLL=0. bit can be used to reduce the number of memory segments and it is Table 13-3.
Table 13-4.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide 13.5 Programming Mode Register: SDRAM Or SyncROM Device When setting up the Mode register that is inside an SDRAM or SyncROM device, or the Configuration register that is inside a SyncFLASH device, the command word that is placed on the address pins shown in Table 13-5 depends on whether a SROM, SDRAM, or SyncFlash is attached.
Note: “RFU” means Reserved for Future Use. Table 13-6, Table 13-7, and Table 13-8 show the bit field values for CASL, RAS, and Burst Length, respectively. Table 13-6. Sync Memory CAS CAS Value SDRAM SFLASH SROM 000 001 010 011 100 101 110 111 Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Reserved 1 2 3 Reserved Reserved Reserved Reserved Reserved 2 3 4 5 6 7 8 13 Table 13-7.
1313 13 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide When using a 16-bit wide external memory bus, the following Read addresses must be used to set up the specified parameters, where H can be 0, C, D, E or F as shown in Table 13-2: • SDRAM default READ Address: 0xH000_6600 — sets WBM=0, TM=0, CAS=3, Sequential, BL=8 • SFLASH default READ Address: 0xH004_6600 — sets WBM=1, TM=0, CAS=3, Sequential, BL=8 • SROM default READ Address: 0xH000_C400 — sets RAS=2, CAS=5, Sequential, BL=8 13.
to the SyncFLASH register and the associated value on the data pins specifies which SyncFLASH register is written. Actually, the value on the data pins specifies a command to the SyncFLASH device such as Write Configuration Register, Lock Block, Block Erase; and the associated value on the address pins specifies either a value that is written to a register or a address location inside the SyncFLASH device.
1313 13 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide Table 13-9. Chip Select Decoding Boot Option (ASDO) A31 A30 A29 A28 Chip select 0 X X X 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 nSDCS3 nSDCS2 nSDCS1 nSDCS0 13.8.2 Address/Data/Control Required by Memory System An independent device configuration register, "SDRAMDevCfg[3:0]", "SDRAMDevCfg[3:0]", "SDRAMDevCfg[3:0]", and "SDRAMDevCfg[3:0]", is provided for each of the four synchronous memory domains.
that AD23 is not used (needed) in either the row or column address, and this demonstrates why the memory map for synchronous memory devices may be non-continuous. Table 13-10.
DS785UM1 Table 13-11.
DS785UM1 Table 13-11.
DS785UM1 Table 13-11.
DS785UM1 Table 13-11.
DS785UM1 Table 13-11.
Table 13-12. Address Bits Used for Chip Select Boot Option (ASDO) A31 A30 A29 A28 Chip select 1 0 0 0 0 nSDCS3 0 1 1 1 1 nSDCS3 X 1 1 1 0 nSDCS2 X 1 1 0 1 nSDCS1 X 1 1 0 0 nSDCS0 13 13.9 Registers The Synchronous Memory controller has seven registers as shown in Table 13-13. The Configuration registers allow software to specify the operating parameters of the Synchronous Memory controller according to the memory device types being used.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide Register Descriptions GlConfig 31 30 CKE Clk Shutdown 15 14 13 29 28 27 26 25 24 23 22 21 20 19 18 17 16 4 3 2 1 0 MRS Initialize RSVD 13 12 11 10 9 RSVD 8 7 6 5 ReArb En LCR SMEM Bust RSVD Address: 0x8006_0004 - Read/Write Default: 0x0000_0000 Definition: The Global configuration register contains general control and status bits.
The CKE bit must be written to ‘0’ before the ClkShutdown bit is written to ‘1’. ReArbEn: Re-arbitration controller Enable - Read/Write Writing a ‘1’ to this bit allows the SDRAM Arbiter to stop the current burst accesses to the external synchronous memory, allow burst accesses from another requester to begin, and later resume the stopped burst accesses.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide Writing a ‘1’ to this bit, in combination with the values of the MRS and LCR bits, cause the Synchronous Memory controller to issue either NOP or PreALL accesses to SDRAM devices as shown in Table 13-4. 0 - See Table 13-14 1 - See Table 13-14 13 Table 13-14.
Definition: The Refresh Timer register is used to specify the period between refresh cycles. Bit Descriptions: RSVD: Reserved. - Unknown During Read Refcnt: Refresh Count - Read/Write The value written to this field specifies, in multiples of the period of HCLK, the time period between refresh cycles. For example, if the period of HCLK is 20 ns, this field should be written to 0x320 (decimal 800) to generate a 16 ms refresh period. On reset, this field defaults to 0x0080 (decimal 128) to generate a 2.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide Latched nCS[7:6] pins values: Asynchronous (ASDO = ‘0’) 11 - 32-bit 10 - 32-bit 01 - 16-bit 00 - 8-bit 13 Synchronous (ASDO = ‘1’) 11 - 32-bit SROM (RAS=2, CAS=5, BL=4) 10 - 32-bit SFLASH (WBM=1, CAS=3, BL=4) 01 - 16-bit SROM (RAS=2, CAS=5, BL=8) 00 - 16-bit SFLASH (WBM=1, CAS=3, BL=4) Note: 8-bit wide bus is not supported for SyncROM or SyncFLASH.
Definition: The four device configuration registers, SDRAMDevCfg[3:0], specify the characteristics of the external synchronous memory device types that are attached to each of the four Synchronous Memory Domains. Only one device type, SDRAM, SyncROM, or SyncFLASH, can be attached to a given domain, but the other domains can have different device types attached.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide When writing to a SyncFLASH device, only single writes (burst-of-one) are allowed.
The value written to this bit specifies a synchronous memory page size of 2 KBytes, or not: 0 - Page size is not 2 KByte 1 - Page size is 2 KByte Only one of the SROM512, SROMLL, and 2KPAGE bits can be ‘1’ at any time. With the exception of SROMLL, these bits always operate in 32-bit memory bus width mode regardless of the setting of External Bus Width bit.
1313 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide The value written to this bit specifies the width of the memory bus: 0 - Width is 32-bits 1 - Width is 16-bits 13 13-26 DS785UM1 Copyright 2007 Cirrus Logic
14UART1 With HDLC and Modem Control Signals 14.1 Introduction UART1 is the collection of a UART block along with a block to support a 9 pin modem interface and a block to support synchronous and asynchronous HDLC protocol support for full duplex transmit and receive. The following sections address each of these blocks. 14.2 UART Overview Transmit and Receive data transfers through UART1 can either be managed by the DMA, interrupt driven, or CPU polled operations.
1414 14 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide The FIFOs can be programmed to be 1 byte deep providing a conventional double-buffered UART interface. The modem status input signals Clear To Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported. The additional modem status input Ring Indicator (RI) is not supported. Output modem control lines, such as Request To Send (RTS) and Data Terminal Ready (DTR), are not explicitly supported.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14 UARTTXD AMBA AMBA APB Interface and Register Block and DMA Interface UARTRXD Figure 14-1.
1414 14 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14.2.1.4 Baud Rate Generator The baud rate generator contains free-running counters which generate the internal x16 clocks and the Baud16 signal. Baud16 provides timing information for UART transmit and receive control. Baud16 is a stream of pulses with a width of one UARTCLK clock period and a frequency of sixteen times the baud rate. 14.2.1.
14.2.1.10 Synchronizing Registers and Logic The UART supports both asynchronous and synchronous operation of the clocks, PCLK and UARTCLK. Synchronization registers and handshaking logic have been implemented, and are active at all times. This has a minimal impact on performance or area. Synchronization of control signals is performed on both directions of data flow, that is, from the PCLK to the UARTCLK domain and from the UARTCLK domain to the PCLK.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14.2.2.1 Error Bits Three error bits are stored in bits [10:8] of the receive FIFO, and are associated with a particular character. See Table 14-1. There is an additional error which indicates an overrun error but it is not associated with a particular character in the receive FIFO. The overrun error is set when the FIFO is full and the next character has been completely received in the shift register.
14.2.3 Interrupts There are five interrupts generated by the UART. Four of these are individual maskable active HIGH interrupts: • UARTMSINTR • UARTRXINTR 1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14 • UARTRTINTR • UARTTXINTR The interrupts are also output as a combined single interrupt UARTINTR. Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in UARTCR. Setting the appropriate mask bit HIGH enables the interrupt.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide • If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single location, the transmit FIFO is asserted HIGH. It is cleared by performing a single write to the transmitter FIFO. The transmit interrupt UARTTXINTR is not qualified with the UART Enable signal, which allows operation in one of two ways. Data can be written to the transmit FIFO prior to enabling the UART and the interrupts.
14.4.1 Overview of HDLC Modes HDLC may operate in one of two basic modes, synchronous or asynchronous. Most configuration options affect both modes identically. Setting the UART1HDLCCtrl.SYNC bit selects synchronous mode and clearing it selects asynchronous mode. In asynchronous mode, each byte is transmitted using standard UART protocol framing (that is, start bit, data, parity, stop bit(s)). In synchronous mode, UART framing is bypassed.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide The receiver utilizes a digital PLL to synchronize to the incoming encoded bit stream. The digital PLL should always successfully lock on to an incoming data stream within two bytes provided that the first two bits of the first byte are either “01” or “10”. Hence, at a minimum, two bytes must precede the final opening flag to insure that the HDLC receiver sees the packet.
Table 14-2. Legal HDLC Mode Configurations (Continued) UART1HDLCCtrl Bits Set Transmit Mode Receive Mode CMAS TXCM RXCM TXENC RXENC SYNC 1 1 - - 1 1 Internal clock Manchester - 1 1 - - 1 External clock External clock 1 1 1 - - 1 Internal clock Internal clock 14 14.4.3 HDLC Transmit In normal operation, the HDLC transmitter either continuously sends flags or holds the transmit pin in a marking state, depending on the setting of the UART1HDLCCtrl.IDLE bit.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide When the last byte of data for a packet is read from the receive FIFO, the HDLC logic sets a number of bits in the UART1HDLCSts depending on the state of the system and the way the packet was terminated. In all cases, the RFC bit and EOF bit are set. If the receive FIFO overflowed while the packet was being received, the ROR bit is also set. If CRC is enabled and the received CRC does not match the calculated one, the CRE bit is set.
incoming address consisting entirely of “1”s, that is, 0xFF or 0xFFFF, will always match, as it is expected to be the broadcast address. For packets whose addresses do not match, the HDLC receiver will generate no interrupts, modify no status bits, and place no data in the receive FIFO. Table 14-3.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14.4.8 DMA The DMA engine may be used with the UART when transmitting and receiving HDLC packets. The transmit and receive channels may operate completely independently. When receiving data in HDLC mode, the DMA channel reads the packet data byte by byte from the RX FIFO. When it reads the final byte, the HDLC RFC interrupt will occur if enabled. However, the DMA channel, which buffers the data, may not write all of the data to memory.
Table 14-4. UART1 Pin Functionality PIN Description RXD0 UART1 input pin TXD0 UART1 output pin CTSn Modem input: Clear To Send DSRn Modem input: Data Set Ready (also used for DCDn Data Carrier Detect) EGPIO[0] Modem output Data Terminal Ready if Syscon register TESTCR[27] RTConGPIO is clear. RTSn Modem output: Ready To Send EGPIO[3] 14 Modem input RIn: Ring Indicator if Syscon register DeviceCfg[25] MODonGPIO is set. Otherwise, RIn is driven low.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14.5.2 Bus Bandwidth Requirements There are two basic ways of moving data to and from the UART FIFOs: • Direct DMA interface - This permits byte-wide access to the UART without using the APB. The DMA block will pack or unpack individual bytes so that it reads or writes full 32-bit words rather than individual bytes. • Accessing the UART via the APB - This requires APB/AHB bus bandwidth.
14.1 Registers UART Register Descriptions UART1Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD DATA Address: 0x808C_0000 - Read/Write Default: 0x0000_0000 Definition: UART Data Register Bit Descriptions: RSVD: Reserved. Unknown During Read.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide UART1RXSts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 OE BE PE FE RSVD 15 14 13 12 11 14 10 9 8 RSVD Address: 0x808C_0004 - Read/Write Default: 0x0000_0000 Definition: UART1 Receive Status Register/Error Clear Register. Provides receive status of the data value last read from the UART1Data. A write to this register clears the framing, parity, break and overrun errors.
FE: Framing Error. When this bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is “1”). This bit is cleared to 0 by a write to UART1RXSts. In FIFO mode, this error is associated with the character at the top of the FIFO.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide FEN: FIFO Enable. 1 - Transmit and receive FIFO buffers are enabled (FIFO mode). 0 - The FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers. STP2: Two Stop Bits Select. 1 - Two stop bits are transmitted at the end of the frame. 0 - One stop bit is transmitted at the end of the frame. The receive logic does not check for two stop bits being received. EPS: Even Parity Select.
Definition: UART Line Control Register Middle. Bit Descriptions: RSVD: Reserved. Unknown During Read. BR: Baud Rate Divisor bits [15:8]. Most significant byte of baud rate divisor. These bits are cleared to 0 on reset.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide UART1Ctrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 LBE RTIE TIE RIE MSIE RSVD 15 14 13 12 14 11 10 9 8 RSVD RSVD UARTE Address: 0x808C_0014 - Read/Write Default: 0x0000_0000 Definition: UART1 Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. LBE: Loopback Enable. If this bit is set to 1, data sent to TXD is received on RXD.
Address: 0x808C_0018 - Read Only Default: 0x0000_0000 Definition: UART Flag Register Bit Descriptions: 14 RSVD: Reserved. Unknown During Read. TXFE: Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the UART1LinCtrlHigh register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. RXFF: Receive FIFO Full.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide CTS: Clear To Send status. This bit is the complement of the UART clear to send (nUARTCTS) modem status input. That is, the bit is 1 when the modem status input is 0.
UART1DMACtrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DMAERR TXDMAE RXDMAE RSVD 15 14 13 12 11 10 9 8 RSVD Address: 0x808C_0028 - Read/Write Default: 0x0000_0000 Definition: UART DMA Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. DMAERR: RX DMA error handing enable. If 0, the RX DMA interface ignores error conditions in the UART receive section.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide Default: 0x0000_0000 Definition: Modem Control Register Bit Descriptions: 14 RSVD: Reserved. Unknown During Read. 0: Must be written as “0”. LOOP: Activate internal modem control loopback function. This internal loopback only affects the hardware handshake signals. Use the UART1Ctrl LBE bit to loopback the serial data.
Definition: Modem Status Register Bit Descriptions: RSVD: Reserved. Unknown During Read. DCD: Inverse of DCDn input pin. Note that this is identical to the DSR device pin. RI: Inverse of RI input pin. DSR: Inverse of the DSRn pin. Note that this is identical to the DCD device pin CTS: Inverse CTSn input pin. DDCD: Delta DCD - DCDn pin changed state since last read. TERI: Trailing Edge Ring Indicator. RI input pin has changed from low to high.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide CMAS: Clock Master: 1 - Transmitter and/or receiver use 1x clock generated by the internal transmitter. 0 - Transmitter and/or receiver use 1x clock generated externally. TXCM: Transmit Clock Mode. 1 - Generate 1x clock when in synchronous HDLC mode using NRZ encoding. 0 - Do not generate clock. This bit has no effect unless TXENC is clear and synchronous HDLC is enabled. RXCM: Receive Clock Mode.
RILEN: Receive Information Lost Interrupt Enable. 0 - RIL interrupt will not occur. 1 - RIL interrupt will occur whenever RIL bit is set. RFLEN: Receive Frame Lost Interrupt Enable. 0 - RFL interrupt will not occur. 1 - RFL interrupt will occur whenever RFL bit is set. RTOEN: Receiver Time Out Interrupt Enable. 0 - RTO interrupt will not occur. 1 - RTO interrupt will occur whenever RTO bit is set. FLAG: Minimum number of opening and closing flags for HDLC TX.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide CRCZ: CRC zero seed 0 - Seed CRC calculations with all ones; that is, 0xFFFF for 16 bit words and 0xFFFF_FFFF for 32 bit words. 1 - Seed CRC calculations with all zeros. Applies to both RX and TX. RXE: HDLC Receive Enable. 0 - Disable HDLC RX. If UART is still enabled, UART may still receive normally. 1 - Enable HDLC RX. TXE: HDLC Transmit Enable. 0 - Disable HDLC TX. If UART is still enabled, UART may still transmit normally.
Default: 0x0000_0000 Definition: HDLC Address Match Value Bit Descriptions: AMV: Address match value. Supports 8-bit and 16-bit address matching. If UART1HDLCCtrl.AME[1:0] is 00b or 11b, this register is not used. UART1HDLCAddMask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 AMSK 15 14 13 12 11 10 9 8 AMSK Address: 0x808C_0214 - Read/Write Default: 0x0000_0000 Definition: HDLC Address Mask Bit Descriptions: AMSK: Address mask value.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide Definition: HDLC Receive Information Buffer Register. This register is loaded when the last data byte in a received frame is read from the receive FIFO. The CPU has until the end of the next frame to read this register, or the RIL bit in the HDLC Status Register is set. Bit Descriptions: 14 RSVD: Reserved. Unknown During Read. BPLLE: Buffered Digital PLL Error. 1 - Receiver aborted last frame because DPLL lost the carrier.
Address: 0x808C_021C - Read/Write Default: 0x0000_0000 Definition: HDLC Status Register. The TFS and RFS bits in this register are replicas of bits in the UART status register. Bit Descriptions: RSVD: Reserved. Unknown During Read. PLLE: Digital PLL Error. (Read Only) 1 - A frame receive was aborted because the DPLL lost synchronization with the carrier. 0 - DPLL has not lost carrier during frame reception. This bit is only valid when set up to receive Manchesterencoded synchronous HDLC.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14 TBY: Transmitter Busy. (Read Only) 0 - TX is idle, disabled, or transmitting an abort. 1 - TX is currently sending a frame (address, control, data, CRC or start/stop flag). RIF: Receiver In Frame. (Read Only) 0 - RX is idle, disabled, or receiving start flags. 1 - RX is receiving a frame. RAB: Receiver Abort. (Read Only) 0 - No abort has been detected for the incoming frame. 1 - Abort detected during receipt of incoming frame.
RFS: Receive FIFO Service request. (Read Only) This bit is a copy of the RIS bit in the UART interrupt identification register. 0 - RX FIFO is empty or RX is disabled. 1 - RX FIFO not empty and RX enabled. May generate an interrupt and signal a DMA service request. TAB: Transmitted Frame Aborted. (Read/Write) Set “1” when a transmitted frame is terminated with an abort. Cleared by writing to a “1” to this bit. TFC: Transmit Frame Complete.
1414 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14 14-36 DS785UM1 Copyright 2007 Cirrus Logic
15UART2 15.1 Introduction UART2 implements a UART interface identical to that of UART1. UART2 does not implement a modem or HDLC interface. For additional details about UART1, refer to Chapter 14, “UART1 With HDLC and Modem Control Signals” on page 14-1. UART2 and the IrDA blocks cooperatively implement a Slow Infrared (SIR) interface. The register interface for each block is separate.
1515 UART2 EP93xx User’s Guide 15 Figure 15-1. IrDA SIR Encoder/decoder Block Diagram 15.2.1.1 IrDA SIR Transmit Encoder The SIR transmit encoder modulates the Non Return-to-Zero (NRZ) transmit bit stream output from the UART. The IrDA SIR physical layer specifies use of a Return To Zero, Inverted (RZI) modulation scheme which represents logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared Light Emitting Diode (LED).
A start bit is detected when the decoder input is LOW. Regardless of being in normal or low-power mode, a start bit is deemed valid if the decoder is still LOW, one period of IrLPBaud16 after the LOW was first detected. This allows a normalmode UART to receive data from a low-power mode UART, which may transmit pulses as small as 1.41 μsec. 15.2.
1515 UART2 EP93xx User’s Guide 15.2.2.1 System/diagnostic Loopback Testing It is possible to perform loopback testing for SIR data by setting the Loop Back Enable (LBE) bit to 1 in the control register UARTCR (bit 7), and setting the SIRTEST bit to 1 in the test register UARTTMR (bit 1). Data transmitted on nSIROUT will be received on the SIRIN input. Note: UART2TMR is the only occasion that a test register needs to be accessed during normal operation. 15 15.2.
15.2.4 Enabling Infrared (Ir) Modes Table 15-1. UART2 / IrDA Modes DeviceCfg Register UART2Ctrl Register IrEnable Register U2EN IonU2 SirEn UARTE EN[1] EN[0] Disabled 0 x 0 0 0 0 UART2 1 0 0 1 0 0 SIR 1 1 1 1 0 1 MIR x 1 0 0 1 0 FIR x 1 0 0 1 1 Mode 15 15.3 UART2 Package Dependency UART2 uses package pins RXD1 and TXD1. Pin RXD1 drives both the UART2 UART input and the UART2 SIR input. However, Syscon register DeviceCfg[28] (IonU2) controls what drives pin TXD1.
1515 UART2 EP93xx User’s Guide Fuartclk <= 4 x Fpclk If the IrDA SIR functionality is required, UARTCLK must have a frequency between 2.7 MHz and 542.7 MHz to ensure that the low-power mode transmit pulse duration complies with the IrDA SIR specification. 15.3.2 Bus Bandwidth Requirements 15 There are two basic ways of moving data to and from the UART FIFOs: • Direct DMA interface - this permits byte-wide access to the UART without using the APB.
15.4 Registers Register Descriptions UART2Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD DATA Address: 0x808D_0000 - Read/Write Default: 0x0000_0000 Definition: UART Data Register Bit Descriptions: RSVD: Reserved. Unknown During Read.
1515 UART2 EP93xx User’s Guide UART2RXSts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 OE BE PE FE RSVD 15 14 13 12 11 15 10 9 8 RSVD Address: 0x808D_0004 - Read/Write Default: 0x0000_0000 Definition: UART Receive Status Register and Error Clear Register. Provides receive status of the data value last read from the UART2Data. A write to this register clears the framing, parity, break and overrun errors. The data value is not important.
FE: Framing Error. When this bit is set to “1”, it indicates that the received character did not have a valid stop bit (a valid stop bit is “1”). This bit is cleared to 0 by a write to UART2RXSts. In FIFO mode, this error is associated with the character at the top of the FIFO.
1515 UART2 EP93xx User’s Guide FEN: FIFO Enable. 1 - Transmit and receive FIFO buffers are enabled (FIFO mode). 0 - The FIFOs are disabled (character mode). (That is, the FIFOs become 1-byte-deep holding registers.) STP2: Two Stop Bits Select. 1 - Two stop bits are transmitted at the end of the frame. 0 - One stop bit is transmitted at the end of the frame. The receive logic does not check for two stop bits being received. EPS: Even Parity Select.
Definition: UART Line Control Register Middle. Bit Descriptions: RSVD: Reserved. Unknown During Read. BR: Baud Rate Divisor bits [15:8]. Most significant byte of baud rate divisor. These bits are cleared to 0 on reset.
1515 UART2 EP93xx User’s Guide UART2Ctrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 LBE RTIE TIE RIE MSIE SIRLP SIREN UARTE RSVD 15 14 13 15 12 11 10 9 8 RSVD Address: 0x808D_0014 - Read/Write Default: 0x0000_0000 Definition: UART Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. LBE: Loopback Enable, for SIR and UART only.
SIRLP: SIR Low Power Mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to “1”, low level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but may reduce transmission distances. SIREN: SIR Enable.
1515 UART2 EP93xx User’s Guide RXFF: Receive FIFO Full. The meaning of this bit depends on the state of the FEN bit in the UART2LinCtrlHigh register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. TXFF: Transmit FIFO Full. The meaning of this bit depends on the state of the FEN bit in the UART2LinCtrlHigh register.
Default: 0x0000_0000 Definition: UART Interrupt Identification and Interrupt Clear Register. Interrupt status is read from UART2IntIDIntClr. A write to UART2IntIDIntClr clears the modem status interrupt. All the bits are cleared to 0 when reset. Bit Descriptions: RSVD: Reserved. Unknown During Read. RTIS: Receive Timeout Interrupt Status. This bit is set to “1” if the receive timeout interrupt is asserted. TIS: Transmit Interrupt Status. This bit is set to “1” if the transmit interrupt is asserted.
1515 UART2 EP93xx User’s Guide ILPDV: IrDA Low Power Divisor bits [7:0]. 8-bit low-power divisor value. These bits are cleared to 0 at reset. The divisor must be chosen so that the relationship 1.42 MHz < IrLPBaud16 < 2.12 MHz is maintained, which results in a low power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.
UART2TMR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 SIRTEST 0 RSVD 15 14 13 12 11 10 9 8 RSVD 0 Address: 0x808D_0084 - Read/Write Default: 0x0000_0000 Definition: UART SIR Loopback Register Bit Descriptions: RSVD: Reserved. Unknown During Read. 0: Must be written as “0”. Unknown During Read. SIRTEST: SIR test enable.
1515 UART2 EP93xx User’s Guide 15 .
16UART3 With HDLC Encoder 1616 Chapter 16 16 16.1 Introduction Note: This chapter applies only to the EP9307, EP9312, and EP9315 processors. UART3 implements both a UART and an HDLC interface identical to that of UART1; it does not implement the modem interface. An additional output signal, TENn, is provided to support RS-485 operation by providing direction control of external data transceivers. The OUT1 and OUT2 signals in the MCR register define the TENn operating mode.
1616 UART3 With HDLC Encoder EP93xx User’s Guide Table 16-2. DeviceCfg Register Bit Functions 16 bit 26 TonG bit 15 HC3IN bit 14 HC3EN bit 12 HC1EN Function x x 0 x External HDLC clock input is driven low. x 0 1 0 External HDLC clock input is driven by EGPIO[3]. x 1 1 0 Internal HDLC clock output drives EGPIO[3]. 1 0 0 0 TENn output drives EGPIO[3]. 16.2.2 Clocking Requirements There are two clocks, PCLK and UARTCLK.
As another example, assume 230,400 baud (the maximum with a UARTCLK equal to 7.3728 Mhz), 5-bit characters, no parity, one stop bit, and no space between characters. There are 7 bits per character, so 230,400 / 7 = 32,914 characters per second. Simultaneous transmitting and receiving implies 65,829 APB characters per second. Using the DMA interface would result in 16,457 AHB accesses per second, while using the APB to access the UART leads to 65,829 bus accesses per second. 16.
1616 UART3 With HDLC Encoder EP93xx User’s Guide a 3-bit status (break, frame and parity) is pushed onto the 11-bit wide receive FIFO • if the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from the UART3Data register, while the corresponding status information can be read by a successive read of the UART3RXSts register.
BE: Break Error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). This bit is cleared to 0 after a write to UART3RXSts. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO.
1616 UART3 With HDLC Encoder EP93xx User’s Guide • UART3LinCtrlMid write, UART3LinCtrlLow write and UART3LinCtrlHigh write. To update UART3LinCtrlLow or UART3LinCtrlMid only: • UART3LinCtrlLow write (or UART3LinCtrlMid write) and UART3LinCtrlHigh write. Bit Descriptions: 16 RSVD: Reserved. Unknown During Read. WLEN: Number of bits per frame: 11 = 8 bits 10 = 7 bits 01 = 6 bits 00 = 5 bits FEN: FIFO Enable. 1 - Transmit and receive FIFO buffers are enabled (FIFO mode).
UART3LinCtrlMid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD 16 BR Address: 0x808E_000C - Read/Write Default: 0x0000_0000 Definition: UART3 Line Control Register Middle Bit Descriptions: RSVD: Reserved. Unknown During Read. BR: Baud Rate Divisor bits [15:8]. Most significant byte of baud rate divisor. These bits are cleared to 0 on reset.
1616 UART3 With HDLC Encoder EP93xx User’s Guide BR: Baud Rate Divisor bits [7:0]. Least significant byte of baud rate divisor. These bits are cleared to 0 on reset. The baud rate divisor is calculated as follows: Baud rate divisor BAUDDIV = (FUARTCLK / (16 * Baud rate)) –1 where FUARTCLK is the UART reference clock frequency. A baud rate divisor of zero is not allowed and will result in no data transfer.
UART3Flag 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 TXFE RXFF TXFF RXFE BUSY DCD DSR CTS RSVD 15 14 13 12 11 10 9 8 RSVD Address: 0x808E_0018 - Read/Write Default: 0x0000_0000 Definition: UART3 Flag Register Bit Descriptions: RSVD: Reserved. Unknown During Read. TXFE: Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the UART3LinCtrlHigh register.
1616 UART3 With HDLC Encoder EP93xx User’s Guide 16 BUSY: UART Busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. DCD: Data Carrier Detect status. This bit is the complement of the UART data carrier detect (nUARTDCD) modem status input.
TIS: Transmit Interrupt Status. This bit is set to 1 if the UARTTXINTR transmit interrupt is asserted, which occurs when the transmit FIFO is not full. It is set to 0 when the transmit FIFO is full. RIS: Receive Interrupt Status. This bit is set to 1 if the UARTRXINTR receive interrupt is asserted, which occurs when the receive FIFO is not empty. It is set to 0 when the receive FIFIO is empty. MIS: Modem Interrupt Status. This bit is set to 1 if the UARTMSINTR modem status interrupt is asserted.
1616 UART3 With HDLC Encoder EP93xx User’s Guide Default: 0x0000_0000 Definition: UART3 DMA Control Register Bit Descriptions: 16 RSVD: Reserved. Unknown During Read. DMAERR: RX DMA error handing enable. If 0, the RX DMA interface ignores error conditions in the UART receive section. If 1, the DMA interface stops and notifies the DMA block when an error occurs. Errors include break errors, parity errors, and framing errors. TXDMAE: TX DMA interface enable.
0: Must be written as “0”. UART3HDLCCtrl 31 30 29 28 RSVD 15 14 13 FLAG 12 27 26 25 24 23 22 21 20 19 18 17 16 CMAS TXCM RXCM TXENC RXENC SYNC TFCEN TABEN RFCEN RILEN RFLEN RTOEN 11 10 9 8 7 6 5 4 3 2 1 0 CRCN CRCApd IDLE RXE TXE TUS CRCE CRCS AME RSVD Address: 0x808E_020C - Read/Write Default: 0x0000_0000 Definition: HDLC Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read.
1616 UART3 With HDLC Encoder EP93xx User’s Guide 16 RXENC: Receive Encoding method. 1 - Use Manchester bit encoding. 0 - Use NRZ bit encoding. This bit has no effect unless synchronous HDLC is enabled. SYNC: Synchronous / Asynchronous HDLC Enable. 0 - Select asynchronous HDLC for TX and RX. 1 - Select synchronous HDLC for TX and RX. TFCEN: Transmit Frame Complete Interrupt Enable. 0 - TFC interrupt will not occur. 1 - TFC interrupt will occur whenever TFC bit is set.
CRCApd: CRC pass through. 0 - Do not pass received CRC to CPU. 1 - Pass received CRC to CPU. IDLE: Idle mode. 0 - Idle-in Mark mode - When HDLC is idle (not transmitting start or stop flags or packets), hold the transmit data pin high. 1 - Idle-in Flag mode - When HDLC is idle, transmit continuous flags. 16 AME: Address Match Enable. Activates address matching on received frames.
1616 UART3 With HDLC Encoder EP93xx User’s Guide UART3HDLCAddMtchVal 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 AMV 15 14 13 12 11 10 9 8 16 AMV Address: 0x808E_0210 - Read/Write Default: 0x0000_0000 Definition: HDLC Address Match Value. Bit Descriptions: AMV: Address match value. Supports 8-bit and 16-bit address matching. If UART3HDLCCtrl.AME is “00” or “11”, this register is not used.
UART3HDLCRXInfoBuf 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 BFRE BROR BCRE BRAB RSVD 15 14 13 12 11 10 RSVD 9 8 BC Address: 0x808E_0218 - Read/Write Default: 0x0000_0000 Definition: HDLC Receive Information Buffer Register. This register is loaded when the last data byte in a received frame is read from the receive FIFO. The CPU has until the end of the next frame to read this register, or the RIL bit in the HDLC Status Register will be set.
1616 16 UART3 With HDLC Encoder EP93xx User’s Guide UART3HDLCSts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD CRE ROR TBY RIF RSVD RAB RTO EOF RFL RIL RFC RFS TAB TFC TFS Address: 0x808E_021C - Read/Write Default: 0x0000_0000 Definition: HDLC Status Register. The TFS and RFS bits in this register are replicas of bits in the UART3 status register. Bit Descriptions: RSVD: Reserved. Unknown During Read.
RAB: Receiver Abort. (Read Only) 0 - No abort has been detected for the incoming frame. 1 - Abort detected during receipt of incoming frame. The most recently read data is the last valid data before the abort. EOF is also set. Note: This bit reflects the status associated with the last character read from the RX FIFO. It changes with reads from the RX FIFO. RTO: Receiver Time Out. Set to “1” whenever the HDLC RX has received four consecutive flags, or four character times of idle or space.
1616 UART3 With HDLC Encoder EP93xx User’s Guide 16 TAB: Transmitted Frame Aborted. (Read/Write) Set “1” when a transmitted frame is terminated with an abort. Cleared by writing to a “1” to this bit. TFC: Transmit Frame Complete. (Read/Write) Set to “1” whenever a transmitted frame completes, whether terminated normally or aborted. Cleared by writing to a “1” to this bit. TFS: Transmit FIFO Service request. (Read Only) This bit is a copy of the TIS bit in the UART interrupt identification register.
17IrDA 17.1 Introduction This module implements the physical layer of an infrared serial port that is compliant with Version 1.1 of the Infrared Data Association (IrDA) standard. It supports communication speeds of up to 4 MBit/s. When combined with analog transducer components, it provides a complete interface between infrared media and an AMBA compliant peripheral bus (APB).
1717 IrDA EP93xx User’s Guide 17.3 Shared IrDA Interface Feature This section describes features common to the MIR and FIR interfaces (the SIR interface has been designed to share the enable register and device pins but is otherwise a separate interface assumed to be controlled by UART2). 17.3.1 Overview 17 The Slow Infrared (SIR) Encoder/Decoder is used to modulate and demodulate serial data using the Hewlett-Packard® Serial Infrared standard (HP-SIR) for bit encoding.
17.3.2.1 General Configuration 17.3.2.1.1 Select Ir Mode The IrEnable register selects which of the three Ir sub-modules is used to operate the IrDA interface. Only one of the three may be active at any one time. The reset value for this register is zero, which disables all three encoder/decoder modules. The bottom two bits of this register select the encoder/decoder module according to the tabulated values: 17 Table 17-1.
1717 IrDA EP93xx User’s Guide 17.3.2.2.2 The Transmit Process This section describes the transmission process in detail. 1. Is last transmission complete? - Ensure that the Infrared peripheral is not currently receiving or transmitting data by reading the RSY (for half-duplex communications) and TBY bits in the IrFlag register. If either is set, postpone the start of transmission. 2. Disable IrDA - If you are changing Ir mode, first disable Ir. To disable IrDA, first clear IrCtrl.RXE and IrCtrl.TXE.
17.3.2.2.3 Sending Packets Which are Not a Multiple of 4 Bytes In Length The transmit FIFO is 32 bits wide. When using polling or interrupts to effect the transfer, loading the FIFO with less than 32 bits would cause extraneous zero bits to be transmitted. This issue is taken care of automatically by the DMA, so no special action is required. However in the case of polling or interrupt-driven transfers, the IrDataTail register is the mechanism used to preload the last 1, 2 or 3 bytes of a frame.
1717 17 IrDA EP93xx User’s Guide Set up DMA Set up a DMA buffer (the buffer should be greater than twice the maximum possible size of received frames). Enable DMA. Alternatively, two buffers may be used which are each the maximum possible frame size long. The DMA would then be programmed to switch between the two buffers. Enable Ir Receive Set the Receive Enable bit (RXE) in IrEnable. 17.3.2.3.
The data word and flags are held in the 39-bit wide receiver FIFO. Reading an IrData word removes both the data and its associated flag bits from the FIFO causing the next word in the FIFO (if present) to be transferred into the IrFlag and data registers. However, all error conditions encountered during a frame are remembered. At the end of frame they can be read form the IrRIB register.
1717 IrDA EP93xx User’s Guide 17.3.3 Control Information Buffering The ARM Core needs several items of information about a received frame that are not held in data DMAed from the receive FIFO, or stored in the DMA controller itself (because the DMA unit may be receiving the next frame by the time the ARM Core starts to work on the frame just completed). The additional information is as follows: • A receive overrun or framing error occurred during frame reception.
1717 IrDA EP93xx User’s Guide 17 Figure 17-1. RZ1/NRZ Bit Encoding Example 17.4.1.2 Frame Format MIR uses a flag (reserved bit pattern) to denote the beginning and end of a frame of information and to synchronize frame transmission. A double flag is used to indicate the start of a frame and a single flag the end. The flag contains eight bits, which start and end with a zero and contain six sequential ones in the middle (01111110b).
1717 IrDA EP93xx User’s Guide 17.4.1.2.1 Address Field The 8 bit address field is used by a transmitter to target a select group of receivers when multiple stations are connected using the infrared link. The address allows up to 255 stations to be uniquely addressed (00000000b to 11111110b). The global address (11111111b) is used to broadcast messages to all stations.
17.4.2 Functional Description Following reset, the MIR is disabled. Reset also causes the transmit and receive buffers and tail register to be flushed (buffers marked as empty). To transmit data in MIR mode, use the following procedure: 1. Set the EN bits in the IrEnable register to 10b for MIR mode. Do not begin data transmission. 2. Before enabling the MIR, the user must first clear any writable or “sticky” status bits that are set by writing a one to each bit.
1717 IrDA EP93xx User’s Guide receive buffer, ignores the remainder of the frame and begins to search for the stop flag. The second byte of the frame can contain an optional control field that must be decoded in software (There is no hardware support within the MIR). Use of a control byte is determined by the user. When the receive buffer contains a word of data, an interrupt or DMA request is signalled.
17.4.2.3 Transmit Operation Immediately after enabling the MIR for transmission, the user may either “prime” the transmit buffer by filling it with data (see section Section 17.4.2 on page 17--11 for details) or allow service requests to cause the CPU or DMA to fill the buffer once the MIR is enabled. Once enabled, the transmit logic issues a service request if its buffer is empty.
1717 IrDA EP93xx User’s Guide 17.5.1 Introduction 17.5.1.1 4PPM Modulation Four position pulse modulation (4PPM) is used for the high-speed transmission rate of 4.0 Mbps. Payload data is divided into data bit pairs (DBPs) for encoding with LSBs transmitted first. Each DBP is represented by one of four symbols (DDs) comprising a single 125 ms pulse within a 500 ms symbol period. The 125 ms quarters of a symbol are known as “chips”.
1717 IrDA EP93xx User’s Guide 17 Receive data sample counter frequency = 6x pulse width, each time-slot sampled on third clock. Figure 17-3. 4PPM Modulation Example 17.5.1.2 4.0 Mbps FIR Frame Format When the 4.0 Mbps transmission rate is used, the high-speed serial/parallel (FIR) interface within the FIR is used along with the 4PPM bit encoding.
1717 17 IrDA EP93xx User’s Guide The preamble, start and stop flags are a mixture of symbols which contain either 0, 1, or 2 pulses within the four time slots. Symbols with 0 and 2 pulses are used to construct flags since they represent invalid data bit pairings (one pulse required per symbol to represent one of four bit pairs).
signalled. The CRC computation logic is preset to all ones before reception/transmission of each frame and the result is inverted before it used for comparison or transmission. Note that unlike the address, control and data fields, the 32 bit inverted CRC value is transmitted and received from least significant byte to most significant and within each byte the least significant nibble is encoded/decoded first.
1717 IrDA EP93xx User’s Guide 17.5.2.2 Receive Operation The IrDA standard specifies that all transmission occurs at half-duplex. This restriction forces the user to enable one direction at a given time; either the transmit or receive logic, but not both. However, the FIR’s hardware does not impose such a restriction. The user may enable both the transmitter and receiver at the same time.
When a framing error is detected all subsequent data in the frame is discarded by the interface and an entry is put into the buffer with the FRE and EOF bits set The data in this buffer entry is invalid. If any two sequential symbols within the data field do not contain pulses (are 0000b), the frame is aborted. The oldest byte in the temporary buffer is moved to the receive buffer (the remaining four buffer entries are discarded).
1717 IrDA EP93xx User’s Guide When unexpected frame termination is selected and an underrun occurs, the transmit logic outputs an abort and interrupts the CPU. An abort continues to be transmitted until data is once again available in the transmit buffer. The FIR then transmits 16 preambles, a start flag and starts the new frame. The remote receiver may choose to ignore the abort and continue to receive data, or to signal the FIR to retry transmission of the aborted frame.
17.5.4 IrDA Integration Information 17.5.4.1 Enabling Infrared Modes Table 17-5. UART2 / IrDA Modes DeviceCfg Register UART2Ctrl Register IrEnable Register Mode U2EN IonU2 SIREn UARTE EN[1] EN[0] Disabled 0 x 0 0 0 0 UART2 1 0 0 1 0 0 SIR 1 1 1 1 0 1 MIR x 1 0 0 1 0 FIR x 1 0 0 1 1 17 17.5.4.2 Clocking Requirements There are four clocks, PCLK, MIRCLK, FIRCLK, and UARTCLK. Version 1.
1717 17 IrDA EP93xx User’s Guide To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less than or equal to four times the frequency of PCLK: F UARTCLK ≤ 4 × FPCLK If the IrDA SIR functionality is required, UARTCLK must have a frequency between 2.7 MHz and 542.7 MHz to ensure that the low-power mode transmit pulse duration complies with the IrDA SIR specification. 17.5.4.
17.6 Registers Register Descriptions IrEnable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 FD MD LBM RSVD 15 14 13 12 11 10 9 8 RSVD EN Address: 0x808B_0000 - Read/Write Default: 0x0000_0018 Definition: IrDA Enable Register. This register selects which Infrared interface module is active. The Medium and Fast modules share common control, flag, and data interfaces while maintaining separate status registers. Bit Descriptions: RSVD: Reserved.
1717 IrDA EP93xx User’s Guide EN: 17 Enable value: 00 - No encoder selected 01 - SIR, 0 to 0.1152Mbit/s data rate, using the UART2 interface 10 - MIR, 0.576 or 1.152Mbit/s data rate, using IrDA interface 11 - FIR, 4.0Mbit/s data rate, using IrDA interface. Note: While the FIR transmit section is enabled, the FD bit is low, and while the MIR transmit section is enabled, the MD bit is low.
TXP: Transmit Polarity Control. 0 - Encoded data is not inverted before being passed to the pins. 1 - Encoded data is inverted before being passed to the pins. RXE: Receive Enable. 0 - Ir receive logic is disabled and clocks are stopped. 1 - Ir receive logic is enabled. TXE: Transmit Enable. 0 - Transmit logic is disabled and clocks are stopped. 1 - Transmit logic is enabled. TUS: Transmit buffer Underrun Select. 0 - Transmit buffer underrun causes CRC, stop flag, and SIP to be transmitted.
1717 17 IrDA EP93xx User’s Guide address of all ones are broadcast frames, and are always matched regardless of the value in the AMV. The AMV may be written at any time, allowing the address match value to be changed during active receive operation. Bit Descriptions: RSVD: Reserved. Unknown During Read. AMV: Address Match Value.
WST: Width Status. 00 - All four bytes in receive buffer are valid. 01 - Least significant byte is valid only. 10 - Least significant two bytes are valid only. 11 - Least significant three bytes are valid only. FRE: FIR Framing Error. 0 - No framing errors encountered in the receipt of FIR data. 1 - Framing error occurred, FIR preamble followed by something other than another preamble or FIR start flag. The data in the buffer is invalid. ROR: Receive buffer Overrun.
1717 IrDA EP93xx User’s Guide Bit Descriptions: DATA: IrDA data word. Values written and sent to the transmit FIFO. Values read are from the receiver FIFO. IrDataTail 31 30 29 28 27 26 25 24 17 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DATA 15 14 13 12 11 10 9 8 DATA Address: 0x808B_0014, 0x808B_0018, 0x808B_001C - Write Only Default: 0x0000_0000 Definition: IrDA Data Tail Register.
IrRIB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 BFRE BROR BCRE BRAB RSVD 15 14 13 12 11 10 RSVD 9 8 BC Address: 0x808B_0020 - Read Only Default: 0x0000_0000 Definition: IrDA Receive Information Register. This register contains 15 read only bits that identify flag and byte count values from the last received frame. The bits are copied from the flag register when the last data in a frame is read from the receive FIFO.
1717 IrDA EP93xx User’s Guide BRAB: Buffered Receiver Abort. 0 - No abort was detected in the last frame. 1 - The last frame was terminated with an abort condition. IrTR0 31 30 29 28 27 26 25 24 17 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD BC Address: 0x808B_0024 - Read Only Default: 0x0000_0000 Definition: IrDA Test Register 0. This register indicates the received byte count. Bit Descriptions: RSVD: Reserved. Unknown During Read.
DMAERR: RX DMA error handing enable. If 0, the RX DMA interface ignores error conditions in the IrDA receive section. If “1”, the DMA interface stops and notifies the DMA block when an error occurs. Errors include framing errors, receive abort, and CRC mismatch. TXDMAE: TX DMA interface enable. Setting to “1” enables the private DMA interface to the transmit FIFO. RXDMAE: RX DMA interface enable. Setting to “1” enables the private DMA interface to the receive FIFO.
1717 IrDA EP93xx User’s Guide MISR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RFL RIL RFC RFS TAB TFC TFS RSVD 15 14 13 12 17 11 10 9 8 RSVD Address: 0x808B_0080 - Read/Write Default: 0x0000_0000 Definition: MIR Status Register. Bit Descriptions: RSVD: Reserved. Unknown During Read. RFL: Receive Frame Lost. Set to a “1” when a ROR occurred at the start of a new frame, before any data for the frame could be put into the receive FIFO.
RFS: Receive buffer Service Request (read only). 0 - Receive buffer is empty or the receiver is discarding data or the receiver is disabled. 1 - Receive buffer is not empty and the receiver is enabled, DMA service request signaled. TAB: Transmit Frame Aborted. Set to “1” when a transmitted frame is terminated with an abort. This will only occur if the TUS bit is set in the IrCtrl register. Writing a “1” to this bit clears it. TFC: Transmitted Frame Complete.
1717 IrDA EP93xx User’s Guide 17 RFC: RFC mask bit. When high, the MIR RFC status can generate an interrupt. RFS: RFS mask bit. When high, the MIR RFS status can generate an interrupt. TAB: TAB mask bit. When high, the MIR TAB status can generate an interrupt. TFC: TFC mask bit. When high, the MIR TFC status can generate an interrupt. TFS: TFS mask bit. When high, the MIR TFS status can generate an interrupt.
FISR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RFL RIL RFC RFS TAB TFC TFS RSVD 15 14 13 12 11 10 9 8 RSVD Address: 0x808B_0180 - Read/Write Default: 0x0000_0000 Definition: FIR Status Register. Bit Descriptions: RSVD: Reserved. Unknown During Read. RFL: Receive Frame Lost. Set to a “1” when a ROR occurred at the start of a new frame, before any data for the frame could be put into the receive FIFO.
1717 IrDA EP93xx User’s Guide 17 RFS: Receive buffer Service Request (read only). 0 - Receive buffer is empty or the receiver is discarding data or the receiver is disabled. 1 - Receive buffer is not empty and the receiver is enabled, DMA service request signaled. The bit is automatically cleared when the receive buffer is emptied. TAB: Transmit Frame Aborted. Set to “1” when a transmitted frame is terminated with an abort. This will only occur if the TUS bit is set in the IrCtrl register.
RFC: RFC mask bit. When high, the FIR RFC status can generate an interrupt. RFS: RFS mask bit. When high, the FIR RFS status can generate an interrupt. TAB: TAB mask bit. When high, the FIR TAB status can generate an interrupt. TFC: TFC mask bit. When high, the FIR TFC status can generate an interrupt. TFS: TFS mask bit. When high, the FIR TFS status can generate an interrupt.
1717 IrDA EP93xx User’s Guide 17 17-38 DS785UM1 Copyright 2007 Cirrus Logic
18Timers 18.1 Introduction The timers are used to control timed events in the system. For example, a wait can be inserted by setting the timer value to an appropriate value and waiting for the timer interrupt. The Timers block contains two 16-bit timers, one 32-bit timer and one 40-bit time stamp debug timer. 18.1.1 Features The processor has these timer features: • Two 16-bit timers • Free running • Load based • One 32-bit timer • Free running • Load based • One 40-bit timer • Free running 18.1.
1818 Timers EP93xx User’s Guide 18.1.2.1 Free Running Mode In free running mode, counters TC1 and TC2 will wrap to 0xFFFF when they reach zero (underflow), and continue counting down. Counter TC3 will wrap to 0xFFFFFFFF when it underflows, and continues counting down. 18.1.2.2 Pre-load Mode In pre-load (periodic) mode, the value written to the TC1, TC2 or TC3 Load registers is automatically re-loaded when the counter underflows. This mode can be used to generate a programmable periodic interrupt.
Register Descriptions Timer1Load, Timer2Load 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 Load Address: Timer1 - 0x8081_0000 - Read/Write Timer2 - 0x8081_0020 - Read/Write Reset Value: 0x0000_0000 Definition: The Load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. The timer is loaded by writing to the Load register when the timer is disabled.
1818 Timers EP93xx User’s Guide Definition: The Load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. The timer is loaded by writing to the Load register when the timer is disabled. The Timer Value register is updated with the Timer Load value as soon as the Timer Load register is written to. The Load register should not be written to after the Timer is enabled as this causes the Timer Value register to be updated with an undetermined value.
Address: Timer3 - 0x8081_0084 - Read Only Reset Value: 0x0000_0000 Definition: The Value location gives the current value of the timer. When the Timer Load register is written to, the Value register is also updated with this Load value. Bit Descriptions: Value: Current value of the timer.
1818 Timers EP93xx User’s Guide Timer1Control, Timer2Control, Timer3Control 31 30 29 28 27 26 25 24 18 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 ENABLE MODE RSVD 15 14 13 12 11 10 RSVD 9 8 RSVD CLKSEL RSVD Address: Timer1 - 0x8081_0008 - Read/Write Timer2 - 0x8081_0028 - Read/Write Timer3 - 0x8081_0088 - Read/Write Reset Value: 0x0000_0000 Definition: The Control register provides enable/disable and mode configurations for the timer.
Timer4ValueLow 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Value 15 14 13 12 11 10 9 8 18 Value Address: Timer4 - 0x8081_0060 - Read Only Reset Value: 0x0000_0000 Definition: This read-only register contains the low word of the time stamp debug timer (Timer4). When this register is read, the high byte of the Timer4 counter is saved in the Timer4ValueHigh register. Bit Descriptions: Value: Read Only Low Word of the Timer4 counter.
1818 Timers EP93xx User’s Guide Bit Descriptions: RSVD: Reserved. Unknown during a Read operation. Enable: Read/Write. Enable for Timer4. Value: Read only. High Byte of the Timer4 counter.
19Watchdog Timer 19.1 Introduction The Watchdog Timer provides a mechanism for generating a system-wide reset should the system hang. This functionality allows the Watchdog to recover the system and report the recovery to software. To prevent system-wide reset, software must periodically reset the Watchdog via an APB write operation. It is possible to disable the Watchdog through either hardware or software. The Watchdog timer circuitry consists of a 7-bit counter.
1919 Watchdog Timer EP93xx User’s Guide 19.1.1 Watchdog Activation The Watchdog circuitry may be disabled via software for test purposes on products that do not wish to use a Watchdog timer by writing 0xAA55 to the Watchdog register. The Watchdog may also be re-enabled via software by writing 0xAAAA to the Watchdog register.
Note: A software reset can reset the system without this register losing its contents. 19.1 Registers Table 19-1. Watchdog Timer Register Memory Map Address Name SW locked Type Size Description 0x8094_0000 "Watchdog" No Read/Write 16/3 bits Watchdog Control Register 0x8094_0004 "WDStatus" No Read/Write 7 bits Watchdog Status Storage Register 19 Note: Watchdog registers are intended to be word-accessed only.
1919 Watchdog Timer EP93xx User’s Guide READ ONLY BIT FIELDS 19 PLSDSN: Pulse Disable Not. The Watchdog internal PLSDIS bit monitors the HW_PULSE_DISABLEn latch status in the watchdog module. This provides status of the hardware pulse duration disable function. Active low means that the reset pulse is disabled. OVRID: Software Override of the hardware watchdog disable. The OVRID bit monitors the SW_OVERIDE_HW_DISABLE register status in the watchdog module.
WDStatus 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD 19 STAT Address: 0x8094_0004 - Read/Write Default: 0x0000_0000 Definition: Watchdog status storage register. It can be used for storing your own status, and it can only be cleared by power-on-reset. Bit Descriptions: RSVD: Reserved. Unknown during read. STAT: Watchdog Status bits.
1919 Watchdog Timer EP93xx User’s Guide 19 19-6 DS785UM1 Copyright 2007 Cirrus Logic
20Real Time Clock With Software Trim 20.1 Introduction The Real Time Clock (RTC) is a circuit that keeps track of the system date and time. The RTC operates from the normal device power supply and the 32 kHz input clock. The RTC circuit operates whenever power is applied to the device and the 32 kHz input clock is running. The Real Time Clock section is composed of two blocks - Real Time Clock and the RTC TRIM. The RTC module provides second level precision for internal time keeping.
2020 Real Time Clock With Software Trim EP93xx User’s Guide 20.1.1.1 Software Compensation The 1 Hz clock is generated by running a programmable counter clocked by the 32.768 KHZ crystal oscillator reference. If the crystal reference and oscillator were perfect, a counter that counted 32768 clocks would provide a 1 Hz reference. However, the counter pre-load value is programmable to allow inaccuracies in the crystal and oscillator circuit.
20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component The manufacturing tester measures the oscillator output to be 33,455.870 Hz. For the integer portion, 33,455 - 32,768 is 687 cycles over the nominal frequency of the crystal. The integer pre-load value for the counter should always be chosen so that the actual clock frequency is faster than the value needed to generate a 1 Hz reference. Therefore, the RTCSWComp.
2020 Real Time Clock With Software Trim EP93xx User’s Guide 20.1.2 Reset Control The RTC block level reset operation is a bit complicated. The reset strategy is for the timekeeping part of the RTC to survive a system reset, and only be initialized by a power-on reset. The RTC interrupt enable is cleared by a user reset, so that a time count match (alarm interrupt) would disable with system reset.
RTCMatch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RTCMR 15 14 13 12 11 10 9 8 20 RTCMR Address: 0x8092_0004 - Read/Write Default: 0x0000_0000 Definition: RTC Match Register. Contain the 32 bit match value. When the RTCData value equals the RTCMatch value the RTC will generate an interrupt if the RTCCtrl.MIE bit is set to “1”. Bit Descriptions: RTCMR: Match value.
2020 Real Time Clock With Software Trim EP93xx User’s Guide RTCLoad 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RTCLR 15 14 13 12 11 10 9 8 20 RTCLR Address: 0x8092_000C - Read/Write Default: 0x0000_0000 Definition: RTC Load Register. Contains the 32 bit load value. Data written to this register is transferred to the RTCData on the next 1 Hz tick. Bit Descriptions: RTCLR: Load value.
RTCSWComp 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 13 12 11 21 20 19 0 10 9 8 7 6 5 18 17 16 1 0 DEL 4 3 2 20 INT Address: 0x8092_0108 - Read/Write Default: 0x0000_7FFF Mask: 003F_FFFF Definition: RTC Software Compensation Register. Bit Descriptions: RSVD: Reserved. Unknown During Read. 0: Must be written as “0”. DEL: Number of clocks to delete. This value determines the number of 32.768 KHZ clocks to delete every 32 seconds for compensating the oscillator.
2020 Real Time Clock With Software Trim EP93xx User’s Guide 20 20-8 DS785UM1 Copyright 2007 Cirrus Logic
21I2S Controller 21.1 Introduction The I2S controller is used to stream serial audio data between the external I2S CODECs’, ADCs/DACs, and the ARM Core. It consists of 3 transmitter channels and 3 receiver channels. Each channel handles a single stereo stream. The transmitter and receiver are completely independent of each other and are programmed separately. Each channel (RX and TX) has its own set of addressable registers which allows access through the ARM APB or DMA accesses.
2121 I2S Controller EP93xx User’s Guide Table 21-1. I2S Controller Input and Output Signals Signal Name Type lrck sck sdi0 sdi1 sdi2 sdo0 sdo1 sdo2 IN IN IN IN IN OUT OUT OUT 21 Description Left/right Word Audio slave clock. Audio bit slave clock.
• Supports 16/24/32 bit word lengths. • Programmable left/right word clock polarity on the serial frame. • Programmable Bit Clock polarity. • Programmable data validity, that is, data valid on the rising/negative edge of the bit clock. • Programmable first data bit position (I2S or non-I2S format). 21 • Programmable Left or Right data word justification • Programmable data shift direction, that is, MSB or LSB transmitted first. • Data underflow detection, that is, re-transmission of old data.
2121 I2S Controller EP93xx User’s Guide these two words will occupy positions 0 and 1 in the FIFO. The FIFO now contains one complete left / right stereo sample. The words written by the programmer must always be right justified when writing 16-bit and 24-bit values. If the programmer writes another left and right stereo sample to the I2STX0Lft and I2STX0Rt registers respectively, these words are loaded into the FIFO and will occupy positions 2 and 3.
The I2S transmit and receive channels should be disabled before changes are made to the control registers. Once the new configuration has been set, the channels can be re-enabled following the specified start order. If a channel is enabled while the FIFO is empty, no samples are read from the FIFO. The I2S controller will parallel load whatever is currently in the left holding register into the shift register.
2121 I2S Controller EP93xx User’s Guide • Programmable first data bit position. that is, I2S or non-I2S format. • Programmable left or right data word justification. • Programmable data shift direction, that is, MSB or LSB received first. • Data overflow detection. • Clock domain synchronization. 21 • DMA accesses. The basic operation of the I2S receiver is that data is serially shifted in to form a pair of left / right words. This pair of words is written to a FIFO, which the ARM will read. 21.3.
Descriptions” on page 448.) Note that both left and right sample registers must be read for the I2S controller to consider the location to be free and modify the internal counter. If the programmer attempts to read from the FIFO while it is empty, the contents that were last read from the FIFO will be put onto the APB bus. The FIFO read pointer is not updated and stays pointing to the same location. The FIFO underflow flag in the Global Control Status register is asserted.
2121 I2S Controller EP93xx User’s Guide order to generate a set of audio clocks, LRCK (word clock) and SCLK (bit clock). The control bits required are: • Master Mode Enable. (i2s_mstr_clk_cfg[0]) • Word Length Control (i2s_mstr_clk_cfg[2:1]) • Bit Clock Polarity (i2s_mstr_clk_cfg[3]) • Not Bit Clock Gating (i2s_mstr_clk_cfg[4]). 21 • Bit Clock Rate (i2s_mstr_clk_cfg[6:5]) These control bits come from the TX and the RX clock configuration registers and the word length registers.
Table 21-4. I2SClkDiv SYSCON Register Effect on I2S Clock Generation (Continued) Function ORIDE=1 Output Data Bit Align to SCLK Edge ORIDE=0 When SPOL=1 and i2s_mstr_clk_cfg[3]=0, transition of output data bit and LRCK align to falling edge of SCLK When SPOL=0 and i2s_mstr_clk_cfg[3]=1, transition of output data bit and LRCK align to rising edge of SCLK; The output data bit is always a halfcycle later to the SCLK edge which aligns to LRCK transition.
2121 21 I2S Controller EP93xx User’s Guide LRCKX 32 pulses 2 I S word size = 32 32 pulses ............... Bitclk ............... 24 pulses I2S word size = 24 24 pulses .......... Bitclk .......... 16 pulses I2S word size = 16 16 pulses .......... Bitclk .......... Figure 21-2. Bit Clock Generation Example 21.5.2 Example of Right Justified LRCK format Figure 21-3 shows the frame format for Right Justified data. The word length is 16 in this case and the MSB is transmitted first.
• TX2 FIFO empty. • TX underflow. The first three can have their interrupt level determined by I2STXCtrl[0]. If this bit = 1, then the FIFO empty interrupt will occur when the FIFO is empty. If this bit = 0, then the FIFO empty interrupt will occur when the FIFO is half empty. All four are combined and are maskable with the TX interrupt register enable bit, I2STXCtrl[1]. 21 The FIFO empty internal interrupts are cleared if the FIFO’s are filled with data or the corresponding channel is disabled.
2121 21 I2S Controller EP93xx User’s Guide Table 21-6. FIFO Flags FIFO Flag Transmitter Receiver FIFO empty FIFO full FIFO overflow FIFO underflow Interrupt and status bit Status Sticky bit Interrupt and status bit Status bit. Interrupt and status bit Interrupt and status bit Sticky bit 21.7 Registers 21.7.1 I2S TX Registers Table 21-7 summarizes the register set in the Transmitter. Each of the registers listed are addressable.
I2S TX Register Descriptions I2STX0Lft 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_tx0_left 15 14 13 12 11 10 9 8 7 21 i2s_tx0_left Address: 0x8082_0010 - Read/Write Default: 0x0000_0000 Definition: Transmit left data word for channel 0. Bit Descriptions: i2s_tx0_left: Transmit left data word for channel 0.
2121 I2S Controller EP93xx User’s Guide I2STX1Lft 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_tx1_left 15 14 13 12 11 10 9 8 21 7 i2s_tx1_left Address: 0x8082_0018 - Read/Write Default: 0x0000_0000 Definition: Transmit left data word for channel 1. Bit Descriptions: i2s_tx1_left: Transmit left data word for channel 1.
I2STX2Lft 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_tx2_left 15 14 13 12 11 10 9 8 7 21 i2s_tx2_left Address: 0x8082_0020 - Read/Write Default: 0x0000_0000 Definition: Transmit left data word for channel 2. Bit Descriptions: i2s_tx2_left: Transmit left data word for channel 2.
2121 I2S Controller EP93xx User’s Guide I2STXLinCtrlData 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 Left_Right_Justify TXUF_REPEAT_SAMPLE TXDIR RSVD 15 14 13 12 11 10 21 9 8 7 6 RSVD Address: 0x8082_0028 - Read/Write Default: 0x0000_0000 Definition: Line Control Data Register Bit Descriptions: RSVD: Reserved. Unknown During Read. Left_Right_Justify: Determines how the data word is justified when being transmitted on the sdo line output.
Definition: Transmit Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. TXUFIE: Transmit interrupt enable. Active high TXEMPTY_int_level:Transmit empty interrupt level select. 0 - Generate interrupt when FIFO is half empty. 1 - Generate interrupt when FIFO is empty.
2121 21 I2S Controller EP93xx User’s Guide Default: 0x0000_0000 Definition: TX0 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read. i2s_tx0_EN: TX0 Channel Enable I2STX1En 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 7 RSVD i2s_tx1_EN Address: 0x8082_0038 - Read/Write Default: 0x0000_0000 Definition: TX1 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read.
Definition: TX2 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read. i2s_tx2_EN: TX2 Channel Enable 21 21.7.2 I2S RX Registers 2 The following table summarizes the register set in the I S Receiver block. Each of the registers listed are addressable. The left and right data registers for channels 0, 1 and 2 can be accessed by both APB and DMA accesses. The remaining registers are concerned with control/status information and can be only accessed through the APB bus. Table 21-8.
2121 21 I2S Controller EP93xx User’s Guide 0x0000_0000 Definition: Receive left data word for channel 0. Bit Descriptions: i2s_rx0_left: Receive left data word for channel 0. I2SRX0Rt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_rx0_right 15 14 13 12 11 10 9 8 7 i2s_rx0_right Address: 0x8082_0044 - Read Only Default: 0x0000_0000 Definition: Receive right data word for channel 0.
I2SRX1Rt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_rx1_right 15 14 13 12 11 10 9 8 7 21 i2s_rx1_right Address: 0x8082_004C - Read Only Default: 0x0000_0000 Definition: Receive right data word for channel 1. Bit Descriptions: i2s_rx1_right: Receive right data word for channel 1.
2121 I2S Controller EP93xx User’s Guide I2SRX2Rt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_rx2_right 15 14 13 12 11 10 9 8 21 7 i2s_rx2_right Address: 0x8082_0054 - Read Only Default: 0x0000_0000 Definition: Receive right data word for channel 2. Bit Descriptions: i2s_rx2_right: Receive right data word for channel 2.
RXDIR: Receive data shift direction. 0 - MSB first 1 - LSB first I2SRXCtrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 21 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD 1 0 ROFLIE RXFull_int_level Address: 0x8082_005C - Read/Write Default: 0x0000_0000 Definition: Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. ROFLIE: Receive interrupt enable. Active high RXFull_int_level: Rx full interrupt level select.
2121 21 I2S Controller EP93xx User’s Guide Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. WL: Receive Word Length. 00 - 16 bit mode 01 - 24 bit mode 10 - 32 bit mode I2SRX0En 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 7 RSVD i2s_rx0_EN Address: 0x8082_0064 - Read/Write Default: 0x0000_0000 Definition: RX0 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read.
Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. i2s_rx1_EN: RX1 Channel Enable I2SRX2En 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 7 RSVD i2s_rx2_EN Address: 0x8082_006C - Read/Write Default: 0x0000_0000 Definition: RX2 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. i2s_rx2_EN: RX2 Channel Enable 21.7.
2121 I2S Controller EP93xx User’s Guide I2S Configuration and Status Register Descriptions I2STXClkCfg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 i2s_tx_nbcg i2s_mstr i2s_trel i2s_tckp i2s_tlrs RSVD 21 15 14 13 12 11 10 9 8 RSVD 7 i2s_tx_bcr Address: 0x8082_0000 - Read/Write Default 0x0000_0000 Definition: Transmitter clock configuration register. Bit Descriptions: RSVD: Reserved. Unknown During Read.
i2s_mstr: Defines if the TX Audio clocks are slave or master. 0 - slave mode. 1 - master mode. i2s_trel: Determines the timing of the lrckt with respect to the sdox data outputs. 0 - Transition of lrckt occurs together with the first data bit. 1 - Transition of lrckt occurs one bitclk cycle before the first sdox data bit. This is I2S format. i2s_tckp: Defines polarity of the TX bitclk. 1 - Positive clock polarity.
2121 I2S Controller EP93xx User’s Guide i2s_rx_bcr: RX bit clock rate. 00 - I2SRXClkCfg[4] defines the bit clock generation. 01 - Bit clock rate is fixed at 32x. Word length is ignored. 10 - Bit clock rate is fixed at 64x. Word length is ignored. 11 - Bit clock rate is fixed at 128x. Word length is ignored. i2s_rx_nbcg: Defines RX not bit clock gating mode. 21 If I2SRXClkCfg[5:6] = 00, this bit defines the bit clock rate, otherwise ignored. Bit clock rate = 32x if word length is 16.
2121 I2S Controller EP93xx User’s Guide 21.7.
2121 I2S Controller EP93xx User’s Guide 21 Tx1_overflow: when = 1, the tx1 FIFO is full and an attempt has been made to write data to it by the APB or DMA. This bit is cleared by writing a 0 to it. Tx2_overflow: when = 1, the tx2 FIFO is full and an attempt has been made to write data to it by the APB or DMA. This bit is cleared by writing a 0 to it. Rx0_underflow: when = 1, the rx0 FIFO is empty and an attempt has been made to read data from it by the APB or DMA.
rx2_fifo_empty: when = 1, FIFO is empty, otherwise not empty rx2_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full I2SGlCtrl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 2121 I2S Controller EP93xx User’s Guide 21 6 5 4 3 RSVD 2 1 0 i2s_loopback i2s_ife Address: 0x8082_000C - Read/Write Default: 0x0000_0000 Definition: I2S Global Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read.
2121 I2S Controller EP93xx User’s Guide 21 21-32 DS785UM1 Copyright 2007 Cirrus Logic
22AC’97 Controller 22.1 Introduction The AC’97 Controller includes a 5-pin serial interface to an external audio codec. The ACLink is a bi-directional, fixed rate, serial PCM (Pulse Code Modulation) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC’97 Controller contains logic that controls the AC-Link to the audio codec and an interface to the AMBA APB.
2222 AC’97 Controller EP93xx User’s Guide and all modem data are at the same sampling rate. If the external codec supported the following channels: PCM LEFT, PCM RIGHT, MODEM1, PCM CENTRE, PCM L SURROUND, PCM R SURROUND, PCM LFE, MODEM2 and HSET, then the user would have to program the transmit side of the controller so that all the audio data was in channel 1, modem data in channel 2, and the HSET data in channel 3. The controller could also receive MIC data at a different rate.
transmitted at 48 kHz, the external codec does not have Data Request Disable bits for these slots. Data for transmission on slots 1, 2, and 12 can be obtained from either the channels or the registers SLOT1RXTX, AC97S2Data and AC97S12Data. However, consistent usage of one of these two methods should be maintained. If the slot enable bits are set when receiving the data for slots 1, 2, and 12, the data is stored in the channel and not the SLOT1/2/12RX registers.
2222 22 AC’97 Controller EP93xx User’s Guide 22.2.1.3 RTIS The receive timeout interrupt is asserted when the receive FIFO is not empty and no further data is received over a number of frames. This number is set by the TOC value in the AC97RXCR register. The receive timeout interrupt is cleared when the FIFO becomes empty through reading all the data. 22.2.1.4 TCIS The transmit complete interrupt is asserted when the transmit FIFO is empty and the parallel to serial shifter is empty.
22.2.2.4 GPIOTXCOMPLETE The transmit GPIOTXCOMPLETE interrupt is asserted when all values written to the AC97S12Data have been transmitted. It is cleared when any data is written to the AC97S12Data. 22.2.2.5 SLOT2INT The receive SLOT2INT interrupt is asserted when the AC97S2Data register has new data that has not been read. By reading the data in the AC97S2Data register the SLOT2INT interrupt is cleared. 22.2.2.
2222 AC’97 Controller EP93xx User’s Guide Table 22-2.
Address: AC97DR1 - 0x8088_0000 - Read/Write AC97DR2 - 0x8088_0020 - Read/Write AC97DR3 - 0x8088_0040 - Read/Write AC97DR4 - 0x8088_0060 - Read/Write Definition: The AC97DR registers are read / write data registers that are normally 20 bits wide. In 16-bit compact mode, all 32 available bits are used. This register is zero at reset. Bit Descriptions: RSVD: Reserved. Unknown During Read. DATA: Write - Transmit FIFO: The AC97TXCR register qualifies the data within the TX FIFO.
2222 AC’97 Controller EP93xx User’s Guide Definition: Receive Control Registers. The AC97RXCR registers are read/write registers that are 32 bits. The data contained within the register controls the data slots that are contained within the receive FIFO. The data contained within the RSIZE bits controls the number of zeros that are to be appended to data to make it 20 bits. Should two channels be enabled for the same data slot, then data is taken from, or given to, the lower channel number.
RSIZE: Determines how many bits to a data word. See Table 22-3 for details of the interaction between RSIZE and CM. 00 data is 16 bits 01 data is 18 bits 10 data is 20 bits 11 data is 12 bits Table 22-3.
2222 22 AC’97 Controller EP93xx User’s Guide AC97TXCRx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RSVD 15 14 CM 13 TSIZE 16 FDIS 12 11 10 9 8 7 6 5 4 3 2 1 0 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TEN Address: AC97TXCR1 - 0x8088_0008 - Read/Write AC97TXCR2 - 0x8088_0028 - Read/Write AC97TXCR3 - 0x8088_0048 - Read/Write AC97TXCR4 - 0x8088_0068 - Read/Write Definition: Transmit Control Registers. The AC97TXCR registers are read/write.
CM: Compact mode enable. If the RSIZE value is either “00” or “11” (setting the data word size to 12- or 16-bits) then the CM bit determines whether the two data words are compacted into one 32-bit word, or each is sent in a separate word. If the RSIZE value is either “01” or “10” (setting the data word size to 18- or 20-bits) then the CM bit has no effect. See Table 22-4. 0 - The data is justified into one 32 bit word 1 - The two data words are compacted into one 32-bit word for reading by the CPU.
2222 22 AC’97 Controller EP93xx User’s Guide TX1: FIFO contains SLOT1 data (only use if sampling rate is 48 kHz). Takes precedence over AC97S1DATA. TEN: A “1” written to this bit enables the transmit for this FIFO and enables the PCLK for the respective Channel.
TXBUSY: TXBUSY is set when TEN = “1” AND there is data in the FIFO, OR when data from this FIFO is being sent in the current frame. TXBUSY is cleared at the start of the next frame following the assertion of the corresponding channel’s TXFE flag (the value of TEN is irrelevant). 22 TXFF: Transmit FIFO full flag, active HIGH. This bit is asserted HIGH if the transmit FIFO is full. RXFF: Receive FIFO full flag, active HIGH. This bit is asserted HIGH if the receive FIFO is full.
2222 22 AC’97 Controller EP93xx User’s Guide RTIS: RX Timeout Interrupt Status - If this bit is set to “1”, the timeout FIFO interrupt is asserted. TCIS: TX complete Interrupt Status - If this bit is set to “1”, the transmit FIFO complete interrupt is asserted.
AC97IEx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RIE TIE RTIE TCIE RSVD 15 14 13 12 11 10 9 8 RSVD Address: AC97IE1 - 0x8088_0018 - Read/Write AC97IE2 - 0x8088_0038 - Read/Write AC97IE3 - 0x8088_0058 - Read/Write AC97IE4 - 0x8088_0078 - Read/Write Definition: Interrupt Enable Register. The AC97IE registers control the Interrupt Enables for the FIFOs within the controller. All bits are cleared on reset. Bit Descriptions: RSVD: Reserved.
2222 AC’97 Controller EP93xx User’s Guide next available frame in SLOT1. As both the AC97S1Data and AC97S2Data data are required for writes to the external codec, the AC97S2Data data will only become valid for transmission when the AC97S1Data has been written also. In order to perform a write to the external codec, the AC97S1Data register must be written to after the AC97S2Data register is written.
codec, the AC97S2Data register must be written to before the AC97S1Data register is written. If a power down is required, then the software must write to SLOT1TX location address 0x26, which is recorded by the controller. If the AC97S2Data bit 12 is set, then the controller will go into power down mode. Bit Descriptions: RSVD: Reserved. Unknown During Read. DATA: Read operation: Read data value of the last value written to this register via the AC-Link interface.
2222 AC’97 Controller EP93xx User’s Guide AC97RGIS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SLOT2TX COMPLETE CODEC READY WINT GPIO INT GPIOTX COMPLETE SLOT2RX VALID SLOT1TX COMPLETE RSVD 15 14 13 12 22 11 10 9 8 7 RSVD Address: 0x8088_008C - Read Only Definition: Raw Global Interrupt Status Register.
AC97GIS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SLOT2TX COMPLETE CODEC READY WINT GPIO INT GPIOTX COMPLETE SLOT2R XVALID SLOT1TX COMPLETE RSVD 15 14 13 12 11 10 9 8 7 RSVD Address: 0x8088_0090 - Read Only Definition: Global Interrupt Status. The AC97GIS register is the global interrupt status register. All bits are cleared to zero on reset. Each bit is the logical AND of the corresponding bits in the AC97RGIS register and the AC97IM register.
2222 AC’97 Controller EP93xx User’s Guide AC97IM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SLOT2TX COMPLETE CODEC READY WINT GPIO INT GPIOTX COMPLETE SLOT2RX VALID SLOT1TX COMPLETE RSVD 15 14 13 12 11 22 10 9 8 7 RSVD Address: 0x8088_0094 - Read/Write Definition: Controller Interrupt Enable Register.
Definition: End Of Interrupt Register. The AC’97 End Of Interrupt Register is a write-only register that allows the CODECREADY and WIS interrupts to be cleared. A write to this location clears the interrupt. Bit Descriptions: RSVD: Reserved. Unknown During Read. CODECREADY: CODECREADY Interrupt Status Clear. A write of “1” to this location will clear the CODECREADY interrupt bit. WINT: Wake-up Interrupt Status Clear. A write of “1” to this location will clear the WIS interrupt bit.
2222 AC’97 Controller EP93xx User’s Guide AC97Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFORCER FORCED RESET TIMED RESET 22 RSVD Address: 0x8088_00A0 - Read/Write Definition: Controller Reset Register. The AC’97 Controller RESET register is a read/write register that controls various functions within the AC’97 Controller of the RESET port. All the register bits are cleared to “0” when reset.
AC97SYNC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFORCES FORCED SYNC TIMED SYNC RSVD Address: 0x8088_00A4 - Read/Write Definition: Sync Control Register. The AC’97 Sync Controller register is a read / write register that controls various functions within the AC’97 Controller of the SYNC port. All the register bits are cleared to “0” when reset. Bit Descriptions: RSVD: Reserved. Unknown During Read.
2222 AC’97 Controller EP93xx User’s Guide AC97GCIS 31 30 29 28 27 26 25 24 23 22 21 20 RSVD 15 14 22 13 12 11 AC97ISR4 19 18 17 16 2 1 0 AC97GIS 10 9 8 AC97ISR3 7 6 5 4 AC97ISR2 3 AC97ISR1 Address: 0x8088_00A8 - Read Only Definition: Global Channel Interrupt Status. The AC97GCIS register (AC’97 Global Channel Interrupt Status) is read only, and echoes all the interrupt status registers in the controller.
23Synchronous Serial Port 23 23.1 Introduction The Synchronous Serial Port (SSP) is a master or slave interface for synchronous serial communication with slave peripheral devices that have either Motorola® SPI, National Semiconductor® Microwire™, or Texas Instruments® synchronous serial interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral device. The CPU or DMA reads and writes data and control and status information.
2323 Synchronous Serial Port EP93xx User’s Guide 23.3 SSP Functionality The SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLKOUT from the input clock SSPCLK. Bit rates are supported to 2MHz and beyond, subject to choice of frequency for SSPCLK. The maximum bit rate will usually be determined by peripheral devices. The SSP operating mode, frame format and size are programmed though the control registers SSPCR0, SSPCR1.
23.5.2 Master/Slave Mode To configure the SSP as a master, clear the SSPCR1 register master or slave selection bit (MS) to 0, which is the default value on reset. Setting the SSPCR1 register MS bit to 1 configures the SSP as a slave. When configured as a slave, enabling or disabling of the SSP SSPTXD signal is provided through the SSPCR1 slave mode SSPTXD output disable bit (SOD). 23.5.3 Serial Bit Rate Generation The serial bit rate is derived by dividing down the 7.4 MHz SSPCLK.
2323 Synchronous Serial Port EP93xx User’s Guide 23.5.5 Texas Instruments® Synchronous Serial Frame Format Figure 23-1 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. SCLKOUT / SCLKIN SFRMOUT / SFRMIN SSPTXD / SSPRXD 23 M SB LSB 4 to 16 bits SSPOE Figure 23-1.
23.5.6 Motorola® SPI Frame Format The Motorola SPI interface is a four-wire interface where the SFRMOUT signal behaves as a slave select. The main feature of the Motorola SPI format is that the inactive state and phase of the SCLKOUT signal are programmable through the SPO and SPH bits within the control register, “SSPCR0” on page 23-13. 23.5.6.1 SPO Clock Polarity When the SPO clock polarity control bit is LOW, it produces a steady state low value on the SCLKOUT pin.
2323 Synchronous Serial Port EP93xx User’s Guide SCLKOUT / SCLKIN SFRMOUT / SFRMIN SSPRXD LS B 23 M SB LSB M SB 4 to 16 bits SSPOE (=0) SSPTXD LS B M SB LSB M SB Figure 23-4.
23.5.8 Motorola SPI Format with SPO=0, SPH=1 The transfer signal sequence for Motorola SPI format with SPO=0, SPH=1 is shown in Figure 23-5, which covers both single and continuous transfers. SCLKOUT / SCLKIN SFRMOUT / SFRMIN SSRXD 23 Q M SB LS B Q 4 to 16 bits SSPOE SSTXD 2323 Synchronous Serial Port EP93xx User’s Guide MS B LS B Figure 23-5.
2323 Synchronous Serial Port EP93xx User’s Guide 23.5.9 Motorola SPI Format with SPO=1, SPH=0 Single and continuous transmission signal sequences for Motorola SPI format with SPO=1, SPH=0 are shown in Figure 23-6 and Figure 23-7. SCLKOUT / SCLKIN 23 SFRMOUT / SFRMIN SSPRXD MS B LS B Q 4 to 16 bits SSPOE MS B SSPTXD LS B Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 Note: In Figure 23-6, Q is an undefined signal.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SFRMOUT master signal being driven LOW, which causes slave data to be immediately transferred onto the SSPRXD line of the master. The master SSPTXD output pad is enabled. One half period later, valid master data is transferred to the SSPTXD line. Now that both the master and slave data have been set, the SCLKOUT master clock pin becomes LOW after one further half SCLKOUT period.
2323 Synchronous Serial Port EP93xx User’s Guide • when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling the SCLKOUT pad (active LOW enable) • when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling the SCLKOUT pad (active LOW enable). If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SFRMOUT master signal being driven LOW. The master SSPTXD output pad is enabled.
Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device. During this transmission, no incoming data is received by the SSP.
2323 Synchronous Serial Port EP93xx User’s Guide SCLK SFRM SSPTXD 23 MSB LSB LSB 8-bit control SSPRXD 0 MSB MSB LSB 4 to 16 bits output data Figure 23-10. Microwire Frame Format (Continuous Transfers) 23.5.11.1 Setup and Hold Time Requirements on SFRMIN with Respect to SCLKIN in Microwire Mode In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SCLKIN after SFRMIN has gone LOW.
23.6 Registers The SSP registers are shown in the following table. Table 23-1. SSP Register Memory Map Description Type Width Reset value Name Description 0x808A_0000 0x808A_0004 Read/write Read/write 16 8 0x0000 0x00 SSPCR0 SSPCR1 0x808A_0008 Read/write 16 0x0000 SSPDR 0x808A_000C 0x808A_0010 Read Read/write 7 8 0x00 0x00 SSPSR SSPCPSR 0x808A_0014 Read 3 0x0 SSPIIR/ SSPICR - - - - Control register 0. Control register 1. Receive FIFO (Read)/ Transmit FIFO data register (Write).
2323 Synchronous Serial Port EP93xx User’s Guide 23 SCR: Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the SSP. SCR is a value from 0 to 255. This provides the secondary divide of (1+SCR) after a pre divide of CPSDVSR (ranging from 2 to 254) SPH: SCLKOUT phase (applicable to Motorola SPI frame format only). SPO: SCLKOUT polarity (applicable to Motorola SPI frame format only).
Default: 0x0000_0000 Definition: SSPCR1 is the control register 1 and contains six different bit fields, which control various functions within the SSP. Bit Descriptions: RSVD: Reserved. Unknown During Read. SOD: Slave-mode output disable. This bit is relevant only in the slave mode (MS=1). In multiple-slave systems, it is possible for an SSPMS master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line.
2323 23 Synchronous Serial Port EP93xx User’s Guide RIE: Receive FIFO interrupt enable: 0 - Receive FIFO half-full or more condition does not generate the SSPRXINTR interrupt. 1 - Receive FIFO half-full or more condition generates the SSPRXINTR interrupt. SSPDR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 DATA Address: 0x808A_0008 - Read/Write Default: 0x0000_0000 Definition: SSPDR is the data register and is 16-bits wide.
DATA: Transmit / Receive FIFO: Read - Receive FIFO Write - Transmit FIFO Note: The user should right-justify data when the SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right justifies.
2323 Synchronous Serial Port EP93xx User’s Guide SSPCPSR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 23 11 10 9 8 RSVD CPSDVSR Address: 0x808A_0010 - Read/Write Default: 0x0000_0000 Definition: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK should be internally divided before further use. The value programmed into this register should be an even number between 2 and 254.
Definition: The interrupt status is read from the SSP interrupt identification register (SSPIIR). A write of any value to the SSP interrupt clear register (SSPICR) clears the SSP receive FIFO overrun interrupt. Therefore, clearing the RORIE bit in the SSPCR1 register will also clear the overrun condition if already asserted. All the bits are cleared to zero when reset. Bit Descriptions: 23 RSVD: Reserved. Unknown During Read.
2323 Synchronous Serial Port EP93xx User’s Guide 23 23-20 DS785UM1 Copyright 2007 Cirrus Logic
24Pulse Width Modulator 2424 Chapter 24 24 24.1 Introduction Note: The EP9307 processor has one PWM with one output, PWMOUT. Note: The EP9301, EP9302, EP9312, and EP9315 processors each have two PWMs with two outputs, PWMOUT and PWMO1. PWMO1 is an alternate function for EGPIO14.
2424 Pulse Width Modulator EP93xx User’s Guide With those two counters specified, a fixed pulse is generated. The two channels are totally independent. This is a DC-level PWM. Either PWM channel can be utilized to create reoccurring pulses at the PWMx output pins. Depending upon how a PWM is programmed, its output can vary from a continuous level (100% duty-cycle), to a square wave (50% duty-cycle), to a narrow pulse approaching a 0% duty-cycle. Both PWMs offer 16-bit resolution of the input clock signal.
24.2.1.3 Dynamic Programming (PWM is Running) Example Note: Updates will take place at the end of the PWM cycle. Order of programming of the Terminal Count and Duty Cycle is important. See Section 24.2.2 on page 24-3. Table 24-2. Dynamic Programming Steps Step Register Value Program TC value with 659 Program DC value with 131 PWMxTermCnt PWMxDutyCycle 0x0293 0x0081 24 24.2.2 Programming Rules 1.
2424 24 Pulse Width Modulator EP93xx User’s Guide Note: All undefined register bits will be read as 0. Register Descriptions PWMxTermCnt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_TC Address: PWM0TermCnt: 0x8091_0000 - Read/Write PWM1TermCnt: 0x8091_0020 - Read/Write Default: 0x0000_0000 Definition: PWMx Terminal Count Bit Descriptions: PWM_TC: PWMxTermCnt is used to adjust the output frequency of the PWM. PWMxTermCnt gives the PWM up to 16-bit resolution.
Bit Descriptions: PWM_DC: PWM_DC is used in conjunction with PWMxTermCnt to adjust the output duty cycle of PWM. PWMxDutyCycle is double buffered to allow it to be programed statically (PWM is stopped) or dynamically (PWM is running). Programmed dynamically, PWMxDutyCycle is updated at the end of a PWM cycle to prevent any output glitches or errors. Reading the register reflects what was written to it, not the state of the counter.
2424 Pulse Width Modulator EP93xx User’s Guide Default: 0x0000_0000 Definition: PWMx Invert Bit Descriptions: 24 RSVD: Reserved. Unknown During Read. INV: Invert PWM output 0 = Output is not inverted. PWMOUT will output tON first then tOFF, PWMxDutyCycle controls tON 1 = Output is inverted. PWMOUT will output tOFF first then tON, PWMxDutyCycle controls tOFF. PWM_INV is double buffered to allow it to be programmed statically (PWM is stopped) or dynamically (PWM is running).
25Analog Touch Screen Interface 2525 Chapter 25 25 25.1 Introduction Note: The EP9301 and EP9302 processors each support a general 5-bit ADC, but no touch screen . Note: The EP9307, EP9312, and EP9315 processors each support up to an 8-wire touch screen or a general 12-bit ADC. The touch screen controller is a hardware engine that controls scanning for 4, 5, 7, or 8-wire analog resistive touch screens (TS).
2525 Analog Touch Screen Interface EP93xx User’s Guide X+ Y+ XY- X+ Y+ XYSX+ SY+ SXSY- 25 4 WIRE ANALOG RESISTIVE TOUCH SCREEN SCHEMATIC 8 WIRE ANALOG RESISTIVE TOUCH SCREEN SCHEMATIC V+ Z+/VZ-/+ V+ Z+/VZ-/+ sV+ sV- Wiper Wiper 5 WIRE ANALOG RESISTIVE TOUCH SCREEN SCHEMATIC 7 WIRE (5 WIRE WITH FEEDBACK) ANALOG RESISTIVE TOUCH SCREEN SCHEMATIC Figure 25-1.
For 8-wire touch screens, the SX and SY lines are used as the measurement reference for the analog-to-digital converter to provide better resolution during a reading and compensate for any drift in samples due to other factors. A 4-wire analog resistive touch screen is the same as an 8-wire without the SX and SY feedback lines. A 4-wire analog resistive touch screen may be adequate for non-industrial use or small touch screens.
2525 Analog Touch Screen Interface EP93xx User’s Guide Table 25-1.
array scanning and enable the state machine. In determining a touch point, the first axis to be scanned is the X-axis. X and Y axis definitions are arbitrary and must only be coordinated with the code when determining a screen position. For 8-wire and 4-wire implementations, the touch screen X and Y axis positioning should be linear for all checking algorithms to work linearly.
2525 Analog Touch Screen Interface EP93xx User’s Guide TOUCH DETECT SAMPLE X-AXIS DISCHARGE ALL LINES SAMPLE Y-AXIS TOUCH_PRESS SW28 SW29 DAC VDD VDD VDD VDD VBAT 100K SW22 100K SW23 SW8 100K SW22 100K SW22 100K SW22 100K SW23 100K SW23 100K SW23 SW30 25 X+ XY+ Y- SW19 SW19 SW19 SW19 SW11 SW11 SW11 SW11 SW20 SW20 SW20 SW20 SW13 SW13 SW13 A/D CONVERTER SW13 A/D CONVERTER SW21 SW21 SW21 SW0 SW0 SW0 SW0 IN X+ XY+ Y- SW1 SW2 SW3 IN SW1 SW2 SW3 X+ XY+
The algorithm begins by putting the touch screen into its touch detect settling state for up to 1024 μsec as determined by the DLY value in the TSSetup register. After the delay value, the algorithm moves to the touch detect state. The switches in the settling and touch detect states are controlled by the TSDetect register value. The algorithm stays in the touch detect state until a touch is detected. Table 25-2.
2525 Analog Touch Screen Interface EP93xx User’s Guide The difference between this new X value and the last valid X value is then compared against the XMIN value stored in the TSXYMaxMin register (unless the X interrupt pending flag is set). If the difference is less than this value no action is taken, and the algorithm continues by discharging and scanning the Y-axis.
START SET X INT PENDING XLAST = X SETTLING TIME FOR KEY DETECTION WAIT FOR TOUCH PRESS SCAN Y-AXIS SCAN X-AXIS APPLY VOLTAGE TO Y-AXIS APPLY VOLTAGE TO X-AXIS DELAY FOR PRESET SETTLING TIME DELAY FOR PRESET SETTLING TIME TAKE 4,8,16,OR 32 SAMPLES STORING MAX,MIN,AND AVERAGE 25 DISCHARGE ALL FOR PRESET SETTLING TIME DISCHARGE ALL FOR PRESET SETTLING TIME N ABS(MAX-MIN) LESS THAN X DEVIATION or DEVTMR carry? N ABS(MAX-MIN) LESS THAN Y DEVIATION or DEVTMR carry? TAKE 4,8,16,OR 32 SAMPLES STORING
2525 Analog Touch Screen Interface EP93xx User’s Guide The algorithm then would continue by discharging and detecting a valid touch. With no X interrupt pending flag, the algorithm also continues by discharging and detecting a valid touch, but without interrupt generation.
TOUCH DETECT SAMPLE X-AXIS DISCHARGE ALL LINES SAMPLE Y-AXIS TOUCH_PRESS SW28 SW29 DAC VDD VDD VBAT 100K SW22 100K SW23 SW8 SW30 SW19 100K SW22 100K SW22 100K SW23 100K SW23 100K SW23 SW19 SW19 SW11 SW11 SW11 SW11 SW20 SW20 SW20 SW13 A/D CONVERTER SW13 A/D CONVERTER SW20 SW13 A/D CONVERTER SW21 SW21 SW21 SW21 SW0 SW0 SW0 SW0 IN SW1 SW2 SW3 IN V+ VZ+/Z-/+ SW1 SW2 SW3 V+ VZ+/Z-/+ IN V+ VZ+/Z-/+ SW1 SW2 SW3 IN SW2 SW3 SW12 SW12 SW12 SW14 SW14 SW14
2525 Analog Touch Screen Interface EP93xx User’s Guide TOUCH DETECT SAMPLE X-AXIS DISCHARGE ALL LINES SAMPLE Y-AXIS TOUCH_PRESS SW28 SW29 DAC VDD VDD VDD VDD VBAT 100K SW22 100K SW23 SW8 SW30 SW19 25 100K SW22 100K SW22 100K SW23 100K SW23 100K SW23 SW19 SW19 SW11 SW11 SW11 SW11 SW20 SW20 SW20 SW13 A/D CONVERTER SW13 A/D CONVERTER SW20 SW13 A/D CONVERTER SW21 SW21 SW21 SW21 SW0 SW0 SW0 SW0 IN SW1 SW2 SW3 V+ VZ+/Z-/+ IN SW1 SW2 SW3 V+ VZ+/Z-/+ IN SW1 S
The register values for TSDirect can be derived from the switch positions in the diagram. A “1” in the register bit position indicates that the switch is made or closed. When TSSetup.S28EN is low, the TSDirect value for 4- or 8-wire touch press detection should be set to 0x0040_4601. Otherwise, when TSSetup.S28EN is high, the TSDetect value should be 0x1040_4601. And, when TSSetup.S28EN is low, the TSDirect value for 5-wire touch press detection should be set to 0x0042_0601. Otherwise, when TSSetup.
2525 Analog Touch Screen Interface EP93xx User’s Guide The register values for TSDirect can be derived from the switch positions shown in Figure 258. A “1” in the register bit position indicates that the switch is made or closed. Therefore, the TSDirect value for battery sampling should be set to 0x4000_0700, the TSDirect value for the measuring the DAC feedback example should be set to 0x2000_0600, and the TSDirect value for measuring a miscellaneous input example should be set to 0x0000_0601.
25.2.5 Measuring Touch Screen Resistance The analog switch array can be configured to get an approximation of touch screen resistance. This may be useful for advanced touch screen algorithms that either try to determine how hard a touch screen is being pressed, or if it is being pressed in more than one location. The touch screen controller built-in algorithm does not use this feature. More advanced algorithms would need to perform either primary or additional scanning through the APB interface.
2525 Analog Touch Screen Interface EP93xx User’s Guide 25.2.6 Polled and Interrupt-Driven Modes The ADC provides support for synchronous sampling, in both polled mode and interruptdriven mode. In either mode, the touch screen scanning state machine should be disabled by setting bit 15 of the TSSetup register to zero. The ADC decimation filter conversion value appears in the TSXYResult register.
25.3 Registers Table 25-4. Analog Touch Screen Register Memory Map Address Name SW locked 0x8090_0000 TSSetup No Read/Write 26 bits Analog Resistive Touch Screen controller setup control register. 0x8090_0004 TSXYMaxMin No Read/Write 32 bits Analog Resistive Touch Screen controller max/min register. 0x8090_0008 TSXYResult No Read Only Type Size Description 32 bits 25 Analog Resistive Touch Screen controller result register.
2525 Analog Touch Screen Interface EP93xx User’s Guide Mask: 03FF_FFFF Definition: Analog Touch screen Setup and Deviation Register. Bit Descriptions: 25 RSVD: Reserved. Unknown during read. TDTCT: TouchDetect Read only bit. Allows the ARM Core the ability to read the state of the TOUCH_DETECT line. SDLY: Defines the amount of settling time between A / D samples from 3 to 1024 μsec assuming a 1 MHz clock. NSMP: Defines the number of samples averaged per X or Y reading.
TSXYMaxMin 31 30 29 28 27 26 25 24 23 22 21 YMAX[11:4] 15 14 13 12 11 20 19 18 17 16 2 1 0 XMAX[11:4] 10 9 8 7 6 5 YMIN[7:0] 4 3 25 XMIN[7:0] Address: 0x8090_0004 Default: 0x0000_0000 Definition: Analog Touch screen MAX and MIN move Register. Bit Descriptions: YMAX[11:4],XMAX[11:4]:Defines the amount of x-y distance from a previous touch that represents an invalid data point. The user could not move to a new location this many pixels away within the scan time limit.
2525 Analog Touch Screen Interface EP93xx User’s Guide Bit Descriptions: 25 RSVD: Reserved. Unknown during read. SDR: Synchronous Data Ready. This bit is set when new conversion data from the ADC digital filter appears the TSXYResult register. The bit is cleared when the TSXYResult register is read. The bit is always clear unless the touch screen scanning state machine is disabled (TSSetup bit 15 is zero).
SCTL: Analog switch control values for the touch controller touch detect, discharge, sample X, and sample Y states and direct analog switch control when the touch screen controller is disabled. A “1” indicates that the switch is made or closed. A “0” indicates that the switch is open. Table 25-2 contains the values that must be loaded into the switch registers, depending on the type of touch screen being used.
2525 Analog Touch Screen Interface EP93xx User’s Guide TSSetup2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 25 13 RSVD 12 11 10 9 8 7 6 5 4 3 2 1 0 RINTEN S28EN NSIGND DISDEV DTMEN DINTEN DEVINT PINTEN PENSTS PINT NICOR TINT Address: 0x8090_0024 Default: 0x0000_0000 Definition: Touch screen Setup Register #2. Bit Descriptions: RSVD: Reserved. Unknown during read. RINTEN: Synchronous Data Ready Interrupt Enable.
DEVINT: Deviation Interrupt. This is the deviation error interrupt. When the DINTEN and DTMEN bits are set high and an axis fails the deviation test 255 times causing an interrupt, this bit must be written to a “0” to clear the interrupt. PINTEN: Pen up Interrupt Enable. Setting this bit high causes an interrupt when the algorithm first detects a pen up condition. PENSTS: Pen Status. This bit allows access to directly read the status of the pen up / down indicator. Read only. 0 - pen up. 1 - pen down.
2525 Analog Touch Screen Interface EP93xx User’s Guide 25 25-24 DS785UM1 Copyright 2007 Cirrus Logic
26Keypad Interface 2626 Chapter 26 26 26.1 Introduction Note: This chapter applies only to the EP9307, EP9312, and EP9315 processors.
2626 Keypad Interface EP93xx User’s Guide 26.2 Theory of Operation The circuitry scans an array of up to 64 keys. The keys are normally open, single pole contacts arranged in an array of 8 rows by 8 columns. The array may be partially filled. The key array rows are designated as ROW0 through ROW7, and the columns are designated as COL0 through COL7. Any 1 or 2 keys in the array that are pressed are de-bounced and decoded.
COL 0 COL 1 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 KEY 00H KEY 01H KEY 02H KEY 03H KEY 04H KEY 05H KEY 06H KEY 07H KEY 08H KEY 09H KEY 0AH KEY 0BH KEY 0CH KEY 0DH KEY 0EH KEY 1FH KEY 10H KEY 11H KEY 12H KEY 13H KEY 14H KEY 15H KEY 16H KEY 17H KEY 18H KEY 19H KEY 1AH KEY 1BH KEY 1CH KEY 1DH KEY 1EH KEY 1FH KEY 20H KEY 21H KEY 22H KEY 23H KEY 24H KEY 25H KEY 26H KEY 27H KEY 28H KEY 29H KEY 2AH KEY 2BH KEY 2CH KEY 2DH KEY 2EH KEY 2FH KEY 30H KEY 31H KEY 32
2626 Keypad Interface EP93xx User’s Guide • No press for address 0x1B at (ROW3, COL3) The ignored addresses, 0x18 and 0x1B, are greater than the addresses of the two keys detected. The following controller actions occur: • ROW0 is driven low. • When ROW0 is low, COL0 and COL3 are also low due to the current paths formed by the keys pressed. 26 • During the time that ROW1 is low each of the columns (COL0 through COL7) is scanned. • Since COL0 is low the key 0x00 appears to be pressed.
26.2.2 Scan and Debounce Products are scanned based on the KEY_SCAN register value. Each complete array scan starts with ROW7 and then progresses to ROW0, 1, and so on because of the pipelined nature of the key scan controller. Keys in this ROW have precedence and are considered first in the scan order because ROW7 is scanned first. When a key is pressed, it may mechanically bounce for a up to 20 msec.
2626 Keypad Interface EP93xx User’s Guide 26.2.4 Low Power Mode The key scanning block also supports a low power wake-up mode. In this mode, a key press generates a wake up interrupt. The key scan interrupt should be masked. Because the wake up interrupt is asynchronous, and depends on external keypad lines which may have a large capacitance value, glitches may occur on the interrupt when transitioning to low power mode. After transitioning, all clocks to the key scanning circuitry can be shut down.
Address: 0x808F_0000 Default: 0x0000_0000 Definition: Key scan initialization register. Bit Descriptions: 26 RSVD: Reserved. Unknown during read. DBNC: De-bounce start count. This value is used to pre-load the de-bounce counter. The de-bounce counter counts the number of consecutive scans that decoded the same keys. Terminal count for the de-bounce counter is 0xFF. Terminal count indirectly generates a key scan interrupt.
2626 Keypad Interface EP93xx User’s Guide PRSCL: Row/Column counter pre-scaler load value. This value is used to pre-load the RC pre-scale counter. The pre-scale down counter counts the number of 1 MHz clocks for every step of the RC counter. When the pre-scale counter reaches 0, the RC counter steps. A pre-load value of 0x002 will cause the RC counter to step every three clocks.
27IDE Interface 2727 Chapter 27 27 27.1 Introduction Note: This chapter applies only to the EP9312 and EP9315 processors. The IDE interface provides an industry standard connection to ATA/ATAPI compliant devices. A single IDE port is provided which will attach to master or slave devices. The interface will support up to: • 2 Devices • PIO Mode 4 • Multi-word DMA Mode 2 • Ultra DMA Mode 4 The IDE block will use the internal DMA controller to do the data transfers in Multiword DMA and Ultra DMA modes.
2727 IDE Interface EP93xx User’s Guide 27.2.1 Diagrams and State Machines Processor IDE Controller IDE Connector 27 CS0n, CS1n DA[2:0] AHB Bus DD[15:0] DMARQ DMACKn DMA Controller DIORn/HDMARDYn/HSTROBE DIOWn/STOP IORDY/DDMARDYn/DSTROBE INTRQ DASPn Figure 27-1. IDE Interface Signal Connections Table 27-1. IDE Host to IDE Interface Definition IDE Pin Type No.
Table 27-1. IDE Host to IDE Interface Definition (Continued) IDE Pin Type No.
2727 IDE Interface EP93xx User’s Guide For a Write Operation. 1. Write out the register value. 2. Delay as follows, based on the PIO mode. PIO Mode 0 - Delay for 70 ns. PIO Mode 1 - Delay for 50 ns. PIO Mode 2 - Delay for 30 ns PIO Mode 3 - Delay for 30 ns PIO Mode 4 - Delay for 25 ns 27 3. Bring DIOWn high. 4. Delay as follows, based on the PIO mode. PIO Mode 0 - Delay for 290 ns. PIO Mode 1 - Delay for 290 ns PIO Mode 2 - Delay for 290 ns PIO Mode 3 - Delay for 80 ns PIO Mode 4 - Delay for 70 ns 5.
In a write operation, when the DMA controller writes to IDEMDMADataOut for completing the DMA transfer, the state machine toggles DIOWn and drives the data onto the DD bus. In a read operation, when data is filled into IDEMDMADataIn by the host latching in the DD bus at the DIORn rising edge, the state machine sends the DMA request. The DMA transfer is completed when the IDEMDMADataIn register is read by the DMA controller. These two registers should only be written or read by the DMA controller.
2727 IDE Interface EP93xx User’s Guide Machine sees that the incoming versus outgoing data rate is out of balance, it will signal the controlling device to pause the transfer. For both read and write operations it is expected that the DMA controller will get behind and not be able to keep up with the device transfer rate. Thus the net transfer rate is determined by the available DMA controller bandwidth and how fast the DMA completion is acknowledged by interrupt or by reading some DMA transfer counters.
latching of the data. It is calculated that the cycle time of AHB clock has to be smaller than (IDE cycle time)*2/3. For different UDMA speed modes, the minimum AHB clock speeds are listed below. There is no special speed constraint imposed on the design for PIO and MDMA modes. Table 27-2. IDE Cycle Times and Data Transfer Rates UDMA Speed Mode Min. IDE Cycle Time Max. AHB Cycle Time Min. AHB Clock Frequency 0 1 2 3 4 112 ns 73 ns 54 ns 39 ns 25 ns 74.7 ns 48.7 ns 36.0 ns 26.0 ns 16.7 ns 13.4 MHz 20.
2727 IDE Interface EP93xx User’s Guide Table 27-3. Wait State Value for the DMA M2M Register Control.PWSC 27 Wait States: Multi-Word DMA Request Ultra DMA Request Read 0 1 Write 3 2 Note: This is the number of wait states required by the IDE Controller to deassert the DMA Controller request line after each word transfer is complete. Table 27-4.
27.2.7.3.3 Ultra DMA Read from IDE Controller Follow the wait-state number listed in the wait-state table in Table 27-3 and Table 27-4. However, the DMA request will not assert unless there are 4 words present in the read FIFO or the transfer is non-quad aligned and has the last remaining bits of data, so quad-word bursts are permissible if the total Ultra DMA transfer size is quad-word aligned. 27.2.7.3.
2727 IDE Interface EP93xx User’s Guide For both PIO and MDMA modes, the actual throughput is limited by the ARM Core's ability to service requests, not raw bandwidth. For UDMA, the throughput is dependent on the bandwidth available to the DMA controller. 27.3 Registers Table 27-6.
Bit Descriptions: RSVD: Reserved. Unknown during read, ignored during write. CS0n: Chip Select 0 pin output control. CS1n: Chip Select 1 pin output control. DA: Device address output control. DIORn: DIORn pin output control. DIOWn: DIOWn pin output control. DASPn: DASPn pin input state. This signal comes in on the EGPIO[15] pin. Read only. DMARQ: DMARQ pin input state. This signal comes in on the EGPIO[2] pin. Read only. INTRQ: INTRQ pin input state.
2727 27 IDE Interface EP93xx User’s Guide Note: At most, one of the above 3 bits should be set to 1 at any time. If more than one is set, the results will be unpredictable, and the data invalid. MODE: Speed mode number. (0 to 4 defined for PIO, 0 to 2 defined for MDMA, 0 to 4 defined for UDMA). WST: Wait State for Turn. Number of HCLK cycles to hold the data bus after a PIO write operation.
Default: 0x0000_0000 Definition: IDE UDMA Configuration Register. Bit Descriptions: RSVD: Reserved. Unknown during read, ignored during write. RWOP: Read or write operation selection: 0 - Read 1 - Write. UEN: Enable Ultra DMA operation. 1 - to start UDMA 0 - to terminate UDMA by the host. 27 Note: Before setting the UEN bit to enable UDMA operation: 1 - Set or Clear the RWOP bit to configure for a Write or Read operation. 2 - Perform a dummy read of the IDEUDMAOp register.
2727 IDE Interface EP93xx User’s Guide IDEDataIn 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 IDEDD 15 14 13 12 11 10 9 8 27 IDEDD Address: 0x800A_0014 - Read Only Default: 0x0000_0000 Definition: In PIO mode read operation, this register is the Input Data Registers, containing the register contents or the data read from the device. The register is loaded from the DD pins at the positive edge of the DIORn signal.
DMA controller. A write by the host during MDMA data-out operation will erroneously interfere with the MDMA state machine. Any read will return zero. Bit Descriptions: IDEDD: IDE output data in the output buffer in MDMA mode.
2727 27 IDE Interface EP93xx User’s Guide addressed and written by the DMA controller. A write by the host during UDMA data-out operation will erroneously interfere with the UDMA state machine. Any read will return zero. Bit Descriptions: IDEDD: IDE output data at the tail of the output buffer in UDMA mode.
Definition: In UDMA data-out and data-in operations, this register contains status about the output and input signals, state machine status and error reporting. Several bits reflect external pins. Their reset state can vary depending on system implementation and system configuration. Bit Descriptions: RSVD: Reserved. Unknown during read, ignored during write. CS0n: Chip select pin0 status. Should be driven to 1 (deasserted) in UDMA. CS1n: Chip select pin1 status.
2727 IDE Interface EP93xx User’s Guide IDEUDMADebug 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RRDR RRPTR RROE RWDR RWPTR RWOE RSVD 15 14 13 12 11 27 10 9 8 RSVD Address: 0x800A_002C - Read/Write Default: 0x0000_0000 Definition: Debug register to reset some internal signals in the UDMA state machine for debug purpose. Bit Descriptions: RSVD: Reserved. Unknown during read, ignored during writes. RWOE: Reset UDMA write data-out error.
Bit Descriptions: RSVD: Reserved. Unknown during read, ignored during writes. HPTR: Head pointer in the write buffer. TPTR: Tail pointer in the write buffer. EMPTY: Write buffer empty status. HOM: Half or more entries in write buffer filled status. NFULL: Write buffer near full status. FULL: Write buffer full status. CRC: CRC result for data-out operation. Reset to 0x4ABA after finishing UDMA operation.
2727 IDE Interface EP93xx User’s Guide 27 27-20 DS785UM1 Copyright 2007 Cirrus Logic
28GPIO Interface 2828 Chapter 28 28 28.1 Introduction Note: The EP9301 and EP9302 processors each have 18 standard GPIOs and 19 enhanced GPIOs. Note: The EP9307 processor has 30 standard GPIOs and 18 enhanced GPIOs. Note: The EP9312 processor has 31 standard GPIOs and 16 enhanced GPIOs. Note: The EP9315 processor has 31 standard GPIOs and 24 enhanced GPIOs. The General Purpose Input/Output (GPIO) is an Advanced Peripheral Bus (APB) slave module.
2828 GPIO Interface EP93xx User’s Guide Mux Controls Port A Control MUX_IO OE DATA 8 EGPIO[7:0] 8 EP Mux Controls Port B Control 28 MUX_IO OE 8 DATA EGPIO[15:8] 8 EP Mux Controls Port C Control MUX_IO OE 8 DATA ROW[7:0] 8 EP Mux Controls Port D Control MUX_IO OE 8 DATA 8 EP Mux Controls Port E Control MUX_IO OE 8 DATA 8 EP Mux Controls Port F Control MUX_IO OE DATA 8 8 EP Mux Controls Port G Control MUX_IO OE DATA 8 8 EP Mux Controls Port H Control MUX_IO
28.1.1 Memory Map The GPIO base address is 0x8084_0000. All registers are 8 bits wide and are aligned on word boundaries. For all registers, the upper 24 bits are not modified when written and always read zeros. 28.1.2 Functional Description Each port has an 8-bit data register and an 8-bit direction register. The data direction register controls whether each individual GPIO pin is an input or output. Writing to a data register only affects the pins that are configured as outputs.
2828 GPIO Interface EP93xx User’s Guide In order to stop any spurious interrupts that may occur during the programming of the GPIOxINTTYPEx registers, the following sequence should be observed: 1. Disable interrupt by writing to GPIO Interrupt Enable register. 2. Set interrupt type by writing GPIOxINTTYPE1/2 register. 3. Clear interrupt by writing to GPIOxEOI register. 4. Enable interrupt by writing to GPIO Interrupt Enable register.
Enhanced GPIO Ports A, B, and F DDR OE[7:0] OE DATA[7:0] DATA DR TISR 28 OE TESTRDSEL TESTINPSEL 1 1 0 to PRDATA[7:0] EP[7:0] 0 INTEN RAW OE STATUS Register Read Select DB ENA INTERRUPT INTTYPE1 EDGE INTTYPE2 POL IN CONTROL LOGIC CLK ICLK Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic (Ports A, B, F) 28.1.3 Reset All GPIO registers are initialized on system reset.
2828 GPIO Interface EP93xx User’s Guide 28.1.4 GPIO Pin Map All GPIO signals are mapped to device pins. The Syscon DeviceCfg register contains four bits that control mapping of the GPIO Ports to device pins: GonK, EonIDE, GonIDE, and HonIDE. Table 28-1, Table 28-2, Table 28-3, and Table 28-4 show how the GPIO ports map to EP93xx pins depending on these control signals. 28 Table 28-1.
4. EEDAT is the EEPROM data pin. 5. ROW[7:0] are the Key Matrix row pins. 6. COL[7:0] are the Key Matrix column pins. Table 28-3.
2828 GPIO Interface EP93xx User’s Guide Table 28-4.
10. COL[7:0] are the Key Matrix column pins. Note: The various functional modes described in Table 28-4 are selected via bits set in the DeviceCfg register in Syscon. See Chapter 5, “DeviceCfg” on page 5-25 for additional register information. When the GPIO port signals are not explicitly mapped to a device pin, the inputs will continue to monitor the pin while outputs are disconnected.
2828 GPIO Interface EP93xx User’s Guide Table 28-5.
PADR: 0x8084_0000 - Read/Write PBDR: 0x8084_0004 - Read/Write PCDR: 0x8084_0008 - Read/Write PDDR: 0x8084_000C - Read/Write PEDR: 0x8084_0020 - Read/Write PFDR: 0x8084_0030 - Read/Write PGDR: 0x8084_0038 - Read/Write PHDR: 0x8084_0040 - Read/Write Definition: Port x Data Register. Values written to this 8-bit read/write register will be output on port x pins if the corresponding data direction bits are set HIGH (port output). Values read from this register reflect the external state of Port x inputs.
2828 28 GPIO Interface EP93xx User’s Guide PxDIR: Port x direction bits. GPIOxIntEn 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 7 RSVD PxINT Address: GPIOAIntEn: 0x8084_009C - Read/Write GPIOBIntEn: 0x8084_00B8 - Read/Write GPIOFIntEn: 0x8084_0058 - Read/Write Definition: The GPIO Interrupt Enable register controls which bits of port A/B/F are to be configured as interrupts.
The INTTYPE1 register controls what type of INTERRUPT can occur on Port A/B/F. Level sensitive when “0” is written to a bit location (“0” default on reset), edge sensitive when “1” is written to a bit location (the type of edge/level is controlled by the INTTYPE2 register). The user must make sure that the direction of port A/B/F is set to input and the corresponding bit in the GPIO INTERRUPT ENABLE register is set to allow the interrupt. All bits are cleared by a system reset.
2828 GPIO Interface EP93xx User’s Guide GPIOxEOI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RSVD 15 14 13 12 28 11 10 9 8 7 RSVD PxINTC Address: GPIOAEOI: 0x8084_0098 - Write Only GPIOBEOI: 0x8084_00B4 - Write Only GPIOFEOI: 0x8084_0054 - Write Only Definition: In order to clear an edge sensitive interrupt that can occur over port A/B/F, the user must write a data value of “1” to the corresponding bit in the GPIOxEOI register bit.
Bit Descriptions: RSVD: Reserved. Unknown During Read. PxINTDB: Interrupt debounce enable.
2828 GPIO Interface EP93xx User’s Guide IntStsA: 0x8084_00A0 - Read Only IntStsB: 0x8084_00BC - Read Only IntStsF: 0x8084_005C - Read Only Definition: For each port, this register reports the same value as the RawIntStsX register for each bit whose corresponding interrupt is enabled. Bits whose corresponding interrupt is not enabled report “0”. 28 Bit Descriptions: RSVD: Reserved. Unknown During Read. PxINTS: Masked Interrupt Status.
Definition: EEPROM interface pin drive type control. Defines the driver type for the EECLK and EEDAT pins. When set, the corresponding pin is open drain, so that the pin will require an external pull-up. When clear, the corresponding pin is a normal CMOS driver. DATOD controls the EEDAT pin. CLKOD controls the EECLK pin. Bit Descriptions: RSVD: Reserved. Unknown During Read. DATOD: Defines the EEDAT pin output driver. CLKOD: Defines the EECLK pin output driver.
2828 GPIO Interface EP93xx User’s Guide 28 28-18 DS785UM1 Copyright 2007 Cirrus Logic
29Security 29.1 Introduction Security is a generalized architecture consisting of Boot ROM, laser fuses and proprietary circuitry for secure hardware initialization. In the context of this environment, the chip supports multiple digital-rights-management content-protection from several security vendors, (such as Microsoft and InterTrust). It exceeds all the requirements set forth by the Secure Digital Music Initiative and allows for protection of object code as well as content. 29.
2929 Security EP93xx User’s Guide 29.4 Registers This section contains the detailed register descriptions for some of the registers in the Security block. Table 29-1 shows the address map for the registers in this block, followed by a detailed listing for each register. Note: Most Security registers are not documented in this Guide. Please contact Cirrus Logic at www.cirrus.com for additional information regarding security features. 29 Table 29-1.
30Glossary Table 30-1. Glossary Term 30 Definition AC’97 Serial Audio data transmission standard ADC Analog to Digital Converter AMBA Advanced Micro-controller Bus Architecture APB Advanced Peripheral Bus ARM920T ARM9 is the general purpose processor core in the EP93xx processors. ATAPI AT Advanced Packet Interface Buffer A “buffer” refers to the area in system memory that is characterized by a buffer descriptor, that is, a start address and the length of the buffer in bytes.
3030 30 Glossary EP93xx User’s Guide Table 30-1.
Chapter 31 31EP93XX Register List Table 31-1 provides an alphabetical list of the EP93XX registers discussed in this manual. Click on the register name to view a detailed discussion of that register. Table 31-1.
3131 EP93XX Register List EP93xx User’s Guide Table 31-1.
Table 31-1.
3131 EP93XX Register List EP93xx User’s Guide Table 31-1.
Table 31-1.
3131 EP93XX Register List EP93xx User’s Guide Table 31-1.
Table 31-1.
3131 EP93XX Register List EP93xx User’s Guide Table 31-1.
Table 31-1.
3131 EP93XX Register List EP93xx User’s Guide Table 31-1.
Table 31-1.
3131 EP93XX Register List EP93xx User’s Guide Table 31-1.
