User Manual
9-4 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
LCD Interface
9
Latency and access time s w ill need to be calculated prior to selecting an LC D panel to
guarantee available bandwidth for the rest of th e system. It should be noted that the
refresh rate is not affected b y the total n umber of pixels.
Gray Scale
The figure below shows the organization of the video map for all bits-per-pixel
combinations. As seen the in th e diagram, the gray scale b locks represent th e two 32-
bit palette registers. Each palette register represents eight 4-bit nibbles for a total of 16
nibbles.
Gray scale creates an intensity for each of the pixel values stored in memory. Four
bits-per-pixel corresponds to a theoretical color depth of 16. Two bits-per-pixel
corresponds to a c olor depth of fou r and so on. Since gray s cale values 7 and 8 create
the same intensity, the actual color depth for 4bpp is 1 5. The effect is created by
simply controlling the amount of time the pixel remains on. See the Gray scale value
to Color Mapping diagram for more details.
An exam ple of this would be the value 12, th at i s stored in a n ibble in the framebuffer
memory. If the 4 bpp is programmed into the controller, the value 12 is map ped to the
LCD palette register for g ray scale value for pixel value 12, assuming a one-to-one
correspondence between the number 12 in memory, and the intensity (Gray scale
value), this pixel will have a duty cycle of about 11/15 or will be lit approximately
73.3% of the time.
Programming the controller includes the following
• LCDCON: Configuration interface for a specific LCD panel
• PALLSW /PALM SW: Sets the palette registers
• FBADD R: Sets the start location in sy stem mem ory for the LCD frame
buffer
• SYSCON1: LCDEN bit turns LCD controller on (enabled).
Note: LCD controller must not be enabled until the above registers are programmed.