User Manual

EP7309/11/12 User’s Manual - DS508UM4 9-3

LCD Interface

The frame buffer start address begins w ith 0x0000000 within each memory region to

the value programmed with the FBADDR wil l define only the most significant byte of

the start address. For instance, program ming the register with 0xC will define the

frame buffer start address to be 0xC0000000. Th e register can therefore be

programm ed with values from 0x1 to 0xC, depending on the external RAM/SDRA M

memory location. Val ues 0x7 and 0x8 are dedicated s ystem memory for the p rocessor

Boot ROM and internal registers respectively so th ese values are n ot valid for the

LCD frame buffer. This region cannot be used. If internal SRAM is used (FBADDR =

0x6), the amount of storage is limited to 48 Kbytes bu t is accessible. Calculating total

memory requirements will be necessary prior to using this fixed memory region.

The screen is map ped as on c ontiguous block of memory where each horizontal line

of pixels is mapped to a s et of consecutive bytes or words. Pixel 0 represent the LSB in

a word wide access of the fram e buffer memory consistent with little endian

configuration.

LCD DMA Controller

The DMA controller for the LCD controller is dedicated to the controller and is

designed to fetch from the fram e buffer memory and fill a nine-word deep F IFO.

Once the controller is ena bl ed, it will continue to operate without requiring service

from the CPU. The DMA controller will request data when th ere are only 5 words

remaining in the FIFO. The DMA bandwidth can be calculated based on the following

criteria:

•refreshrate

• panel size

•bitsperpixel

1/2 VGA with 4 bpp@ 80 Hz refresh = (640x240) x 4 bp s x 80 Hz = 6. 14 Mbytes/s.

This assumes that the frame buffer is s tored in a 32-bit-wide memory. Sixteen-bit-

widememorycanbeusedwhichwilldoubletheaccesstimeandtheDMAlatency

DMA latency calculations are based on a 32-bit-wide memory. Assuming 1/2 VGA , 5

words for a FIFO fill, 80 Hz refresh rate at 4 bpp, the maximum allowable latency can

only be approxim ately:

(5 words x 32 bits/word)/(640x240x4 bppx80 Hz) = 3.25 µs.

This number represents the worst case latency or the total number of cycles from

when the DMA request appears to when the first DMA data word ac tually becomes

available or is written to the FIFO. DMA has the highest priority in the system so the

FIFO fill will always occur next in sequence.

The maximum number of cycles between a DMA request for data and the first word

seen in the FIFO is 42. At 13 MHz bus speed (77 n s cycle time), the latency i s

approximately 3. 23us. At 18 MH z, the latency is reduced to 2.26 µs. At 36 MHz bus

speed, or 74 MHz internal CPU speed, the number is even further reduce to about

1.49 µs. The calculation is more c omp lex. Th e total number of cycles at 36 MHz is

(12x4) + 7 = 55.