User Manual

8-2 EP7309/11/12 User’s Manual - DS508UM4

SRAM/Expansion Bus Controller

MemConfig1value EQU 0x3c011814 ; CS0-CS3 configuration values

MemConfig2value EQU 0x0000001e ; CS6(Internal SRAM) CS7(Internal Boot ROM)

;*****************************************************************************

;configurenCS0 - nCS3

;*****************************************************************************

;

ldr r1, =MemConfig1value

str r1,[r12,#0x0180] ; MEMCFG1 = 0x8000.0180

;

;*****************************************************************************

;configurenCS4 - nCS5

;*****************************************************************************

;

ldr r1, =MemConfig2value

str r1,[r12,#0x01c0] ; MEMCFG2 = 0x8000.01c0

;

Operational Overview

All c hip selects c a n be configured as 8, 16, or 32-bit wide memory to interface to a

wide range of external hardware. Each chip select has a default address at power on

reset, but c an change based on how the pagetable in the MMU remaps the memory.

At power on reset, the initial setting for the Bus width for all chip selects will depend

on the state of

PE1 and PE0 at that time. Th e software can then reconfigure the c hip

selects. Wait states are programmable from 1-8 additional clocks.

There are tw o internal registers f or program mi ng the chip selects: M EMCF G1 and

MEMCFG2. These registers are described below.

Note: At power-on-reset or system reset, all values are cleared.

There are a total of six chip selects CS0-CS5, that are user controlled to access memory

or devices throughout the system. Programming i ncludes, bus width from 8- 32 bits,

wait states, and bus clock access, in the event that the interface is not asynchronous.

Note: The memory area decode by CS[6] is reserved for on-chip SRAM and does not require

programming. The default configuration is 32-bit wide and no wait states.CS[7] accesses internal boot

ROM and defaults to 8-bit wi de and no wait states. No additional programming is possible.