User Manual
7-4 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
SDRAM Controller
7
SDWIDTH[1:0]: The width of each SDRAM device:
00 = 4 bits
01 = 8 bits
10 = 16 bits
11 = 32 bits
This value is independent of the bus width setting and is
necessary to differentiate the individual devi ces within a bank.
CLKCTL: Control over the SDRAM clock:
0 = SDRAM clock is perm anently enabled except when in standby
mode.
1 = SDRAM clock stops when the EP73xx is put into the
STA NDBY state or SDA CTIVE = ‘0’.
There will b e an additional delay of one clock cycle for any acc ess
request made when the SDRAM clock is stopped.
SDACTIVE: Enables the SDRAM controller:
0 = Disable SDRAM controller
1 = Enable SDRAM controller
Thedefaultstateis‘0’.
SDRAM Refresh Period Register (SDRFPR)
Address: 0x80002340, Read / Write
Definition: SDRFPR is a register containing a 16-bit value representing the
interval between SDRAM refresh commands. The value
programmed is in bus clock cycles. The following example
calculates the value for REFRATE for a 16 µSrefreshperiodwitha
bus clock of 36 MHz:
16E
-6
* 36E
6
= 576
The refresh timer is s et to 256 b y nPOR to ensure a refresh time of
better than 16 µS even at 13 M Hz. This reg ister should not b e
programmed to a valu e below 2. Otherwise, th e bu s may become
locked.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRATE