User Manual

EP7309/11/12 User’s Manual - DS508UM4 7-3
Copyright Cirrus Logic, Inc. 2003
SDRAM Controller
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7
The SDRAM controller will continue to pr ovide refresh cycles at the rate set in
SDRFPR until th e SDACTIVE bit is set to 0 or the CPU is reset.
Byte Masks
Pins PD6 and PD7 are multiplexed with th e SDQM0 and SDQM1 signals, respectively.
ENPD67, bit 10 in the SYSCON3 register, enables pins
PD6 and PD7 as GPIO bits
when set. This is useful in applications which do not involve the SDRAM interface.
When cleared, pins
PD6 and PD7 represent the SDQM0 and SDQM1 output signals
from the SDRAM controller. ENPD67 must be cleared in order to properly use th e
SDRAM i nterface.
SDRAM Register Descriptions
SDRAM Control Register (SDCONF)
Address: 0x8000.2300, Read / Write
Definition: SDRAM Configuration Data Register.
Bit Descriptions:
RSVD: Reserved. Unknown during read.
CASLAT[1:0]: Num ber of clock cycles after CAS before the device is ready f or
reading or writing:
00 = reserved
01 = reserved
10 = C AS latency = 2
11 = CAS latency = 3
The default value is ‘ 10’ for CAS latency = 2.
SDSIZE[1:0]: Indicates the capacity of each SDRAM device:
00 = 16 Mbit
01 = 64 Mbit
10 = 128 Mbit
11 = 256 Mbit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD SDACTIVE CLKCTL SDWIDTH[1:0] SDSIZE[1:0] RSVD CASLAT[1:0]