User Manual

7-2 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
SDRAM Controller
7
Programming Example
;*****************************************************************************
; Sample initialization code for the SDRAM controller on the EDB7312:
;*****************************************************************************
;
ldr r0,=0x80000000 ; internal registers
ldr r3,=0x2000 ; local offset for memory
add r4,r3,r0 ; add & store offset in r4
mov r1,#0x522 ; CASLAT=2, SDSIZE=64 Mb, SDWIDTH=16, CLKCTL=0, SDACTIVE=1
str r1,[r4,#0x300] ; store in SDCONF
mov r1,#0x100 ; REFRATE=7.11 µS at 36 MHz BCLK
str r1,[r4,#0x340] ; store value in SDRFPR
;
Operational Overview
System Initialization
When the EP73xx encou nters a power- on reset or a user reset, the SDRAM controller
is disabled. To configure the SDRAM controller:
1. Before initializing the controller, insure that the ENDP67 bit in the
SYSCON3 register is set to its default value of 0, and the DRAMZ bit in
SYSCON2 is set for the appropriate SDRAM access width.
2. Load the requested refresh rate into the SDRFPR register.
3. Write the SDC ON F with a configuration word c ontaining the desired
CASLAT, SDSIZE, SDW ID TH, and C LKCTL for your SDRAM devices plus
a 1 in the SDACTIVE bit field to activate th e controller.
4. Cache (MMU) must be enabled for the SD RAM memory regions allocated
to the system software.
Immediately after initializing the controller, the SDRAM controller:
1. Sends a PRECHARGE command to all configured SDRAM banks.
2. Sends a LOAD MOD E REGISTER command to all SDRAM devices in all
banks.
3. Loads the mode registers on all SDRAM devices with a configuration word
containing the CAS latency set in the CASLAT bits of SDCONF, a burst
length of 4, and the configuration bits to enable sequential programmed
length bursts.
4. Performs eight CBR (auto) refresh cycles to complete the initialization
sequence.