User Manual

EP7309/11/12 User’s Manual - DS508UM4 7-1

Chapter 7

7SDRAM Controller

Introduction

External SDRAM on the EP7311 an d EP7312 is supported via the SDRAM controller.

It allows industry standar d SDRAM memories to be used within the a ddress space of

the EP73xx w ith no software overhead. The controller is attached to the ARM core

through the inter nal high s peed bus. It operates at a maximu m clock speed of

36.864 MHz (45 MHz when is CPU running at 90 MHz), providing all the necessary

connections to interface to two b anks of SDRAM. For inform ation on implementing

external SDRAM with the EP 7312, see the Application Note, “Interfacing the EP7312

with SDRAM” (AN218). The EP7309 does not include t he SDRAM controller.

Features

The SDRAM controller within the EP7311 and EP7312 p rovides a convenient method

for using inexpensive SDRAM devices as local memory.

It supports:

• Standard NEC or c ompatible devices in s izes of 16 to 256 Mbit, yielding a

total memory capacity of 2 to 64 MByte

•UptotwoexternalbanksofSDRAM

SDCS[0:1],andcontroloffour

internal ban ks for each SDRAM device.

• A programmable bus width for accessing 16 or 32 bit wide banks

• Putting the SDRAM devices into self-refresh mode when th e CP U is put

into Standby

•Quadwordorquadhalfwordaccesseswithbytemaskselectsforshort

reads

• Internal multiplexing of address lines for contiguous memory access

• Automatic JEDEC Standard No. 21-C compliant SDRAM initialization

SDRAM Register List

Table 7-1: SDRAM Registers

Address Name Type Size Description Page

0x8000.2300 SDCONF R/W 16 SDRAM Control Register page 7-3

0x8000.2340 SDRFPR R/W 16 SDRAM Refresh Period Register page 7-4