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EP7309/11/12 User’s Manual - DS508UM4 6-5
Copyright Cirrus Logic, Inc. 2003
Processor Support
66
6
Note: Bold indicates active byte lane.
Values seen ab ove are n ot values stored into memory but what is actually s een on the
memory bus. Given the architecture, only load and store instructions will be affected
by endi aness. For more information, refer to ARM Application Note 61, Big and Little
Endian Byte Addressing.
Word + 2 (H) 11223344 44 33 44 33 44 33 44 33
Word + 3 (H) 11223344 44 33 44 33 44 33 44 33
Word + 0 (B) 11223344 44 44 44 44 44 44 44 44
Word + 1 (B) 11223344 44 44 44 44 44 44 44 44
Word + 2 (B) 11223344 44 44 44 44 44 44 44 44
Word + 3 (B) 11223344 44 44 44 44 44 44 44 44
Table 6-5: Effect on Endianess on Write Operations (Continued)
Address
(W/B)
Register
Contents
Byte Lanes to Memory / Ports / Registers
Big Endian Memory Little Endian Memory
7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24