User Manual

5-10 EP7309/11/12 User’s Manual - DS508UM4

System Registers

Bit Descriptions:

MCDR: Media changed direct read. Th is bit reflects the inverted, non-

latched status of the media changed input.

DCDET: This bit w ill be set if a non-ba ttery o perat e d power sup ply is

powering the system ( it is th e inverted state of the

nEXTPWR

input pin).

WUDR: Wake up direct read. This bit reflects the non-latched state of the

wakeup signal.

WUON: This bit will be set if the system has been brought out of the

Standby State by a rising edge on the wakeup signal. It is cleared

by a s ystem reset or by writing to the HALT or STDBY locations.

DID: Di splay ID nibble. This 4-bit nibble reflec t s the latched state of th e

four LCD data lines. The state of the four LCD data lines is latched

by the LCDEN bit, and so it w i ll always reflect the last state of

these lines before the LCD controller was enabled.

CTS: This bit reflects the current status of the clear to send (CTS)

modem control input to UA RT1.

DSR: This bit reflects th e current status of the data set ready (DSR)

modem control input to UA RT1.

DCD: This bit reflects the current status of the dat a carrier detect (DCD)

modem control input to UA RT1.

UBUSY1: UART1 transmitter busy. This bit is set while UART1 is busy

transmitting data, it is gua ranteed to remain set until the complete

byte has been sent, including all stop bits.

NBFLG: New battery flag. This bit will be set if a low t o high transition has

occu rred on the

nBATCHG input, it is cleared by writing to the

STFCLR location.

RSTFLG: Reset flag. This bit will b e set if the RESET button has been

pressed, forcing the

nURESET input low. It is cleared by writing to

the STFCLR location.

PFFLG: Power Fail Flag. This bit will be set if the system has been reset by

the

nPWRFL input pin, it is cleared by writing to the STFCLR

location.

CLDFLG: Cold start flag. This b it will be set i f the EP73xx has been reset

with a power on reset, it is cleared by writing to the STFCLR

location.

RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that h ave passed

since the last increment of the RTC. It is the output of the divide

by 64 c hain that di vides the 64 Hz tick clock down to 1 Hz for the

RTC. The MSB is th e 32 Hz output, the LSB is the 1 Hz output.