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5-8 EP7309/11/12 User’s Manual - DS508UM4

System Registers

SS2MAEN: Master mode enable for the synchronous serial interface 2. W h en

low, SSI2 will be configured for slave mode operation. Wh en high,

SSI2 will be configured for master mode operation. This bit also

controls the directionality of the interface pins.

OSTB: This bit (operating system timing bit) is for use only with the

13 MHz clock source mode. Normally it will be set l ow, however

when set high it will cause a 500 kHz clock to be generated for the

timers instead of the 541 kHz which would normally be available.

The divider to generate this frequency is not clocked when this bit

is set low.

CLKE NSL:

CLKEN select.Whenlow,theCLKEN signal wi ll be output on the

RUN/CLKEN pin. When high, the RUN signal will be output on

RUN/CLKEN.

BUZFREQ: Selects the hardware source for the

BUZ pin. When set, a fixed

500 Hz (528 Hz in 13 MHz m ode and 612 Hz at 90 MHz) clock is

used as the source. W hen cleared, the overflow bit from timer TC1

is used as the clock signal.

System Control Register 3 (SYSCON3)

Address: 0x8000.2200, Read / Write

Definition: The SYSCON3 system control register is a 11-bit read/write register

which controls some of the general c onfiguration parameters for the

EP73xx as well as the control an d status of internal peripherals. All

bits i n this register are cleared upon system reset (nSYSRES).

Bit Descriptions:

ADCCON: Determ ines whether the A DC Configuration Extension field

SYNCIO[16-31] is to be u sed for ADC configuration data. When

this bit = 0 (default state) the ADC Configuration Byte SYNCIO[0-

7] only is used for backwards compatibility. When this bit = 1, the

ADC Configuration Extension field in the SYNCIO register is

used for ADC Configuration data an d the value in the ADC

Configuration Byte (SYNCIO[0-6]) selects the length of the data

(8-bit to 16-bit).

CLKCTL: This two-bit field determ ines the c lock speed for the ARM720T

core, the clock speed for the memory bus, and the wait state

scaling factor. When operating the CPU from an external 13 MHz

clock, CLKCTL must be set to 00. The following table lists the

options.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD ENPD67 128Fs Reserve

d-0

VERSN (read-only) ADCCK

NSEN

DAISEL CLKCTL

CLKCTL

ADCCO