User Manual

5-6 EP7309/11/12 User’s Manual - DS508UM4

System Registers

ADCKSEL: Microwire/SPI peripheral clock speed select. This two bit field

selects the frequency of the ADC sample clock, which is twice the

frequency of the synchronous serial ADC interface clock. The

table below shows the available frequencies for operation when

the CPU is operated in either PLL mode or in 13 MHz external

clock mode. These bits are also used to select the master m ode

shift clock frequency for the SSI2 interface w hen set into master

mode.

EXCKEN: External expansion clock enable. If this bit is set, the

EXPCLK is

enabled continuously as a free running clock assuming that the

main oscillator is run ning. Refer to CLKCTL bits[1-2] on

SYSCON3.

EXPCLK corresponds to th e m emory bus frequency in

the table provided. This bit should not be left set all the time for

power consumption reasons. If the system enters the Standb y

State, th e

EXPCLK will become undefined. If this bit is clear,

EXPCLK will be active during memory cycles to expansion slots

that have external wait state generation enabled only.

WAKEDIS: Setting this bit d isables waking u p from the Standby State, via the

wakeup input.

IRTXM: IrDA TX mode bit. Th is bit controls the IrDA encoding strategy.

Clearing this bit means that each zero bit tran sm itted is

represented as a pulse of width 3/16th of the bit rate period.

Setting this bit means each zero bit is represented as a pulse of

width 3/ 16th of th e period of 115,200-bit rate clock (i.e., 1.6 ms

regardless of the selected bit rate).

Setting this b it will use less

powe r, but will probably reduce transmission distan ces.

* The p ulse width will be reduced by 22.5% when operating at 90.3168 MHz.

Table 5-3: ADC Sample Clock Settings

ADCKSEL

ADC Sample Frequency (kHz) — SMPCLK ADC Clock Frequency (kHz) — ADCCLK

90 MHz PLL Clock 13 MHz EXTCLK 90 MHz PLL Clock 13 MHz EXTCLK

00 9.8 8 8.4 4.9 4 4.2

01 39.2 32 33.8 19.6 16 16.9

10 156.8 128 135.4 78.4 64 67.7

11 313.6 256 270.8 156.8 128 135.4