User Manual

EP7309/11/12 User’s Manual - DS508UM4 4-13

Interrupt Controller

Interrupt Mask Register 3 (INTMR3)

Address: 0x8000.2280, Read / Write

Definition: This register contains the interrupt mask for the DAI interface. This

interrupt triggers the fast interrupt (FIQ) signal of the ARM720T

core.

Bit Descriptions:

DAIINT: DA I i nterface interrupt. The cause must be determined by reading

the DAI status register. It is mapped to the FIQ interrupt on th e

ARM720T processor.

End-Of-Interrupt Locations

The “End of In terrupt” locations that follow are written to after the appropriate

interrupt has been serviced. The write is performed to clear the interrupt s tatus bi t, so

other interrupts can be serviced. Any value may be written to these locations.

Battery Low End of Interrupt (BLEOI)

Address: 0x8000.0600

Definition: A write to this location will clear the interrupt generated by a low

battery (falling edge of

BATOK with nEXTPWR high).

Media Change End of Interrupt (MCEOI)

Address: 0x8000.0640

Definition: A write to this loc ation will c lear the interrupt generated by a falling

edge of the

nMEDCHG input pin.

Tick End of Interrupt (TEOI)

Address: 0x8000.0680

Definition: A write to this location will clear th e current p ending tick interrupt

and tick watch dog interrupt.

TC1 End of Interrupt (TC1EOI)

Address: 0x8000.06C0

Definition: A write to this loca tion will clear the under flow interrupt gene ra ted

by TC1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD DAIINT