User Manual

EP7309/11/12 User’s Manual - DS508UM4 4-11

Interrupt Controller

Interrupt Status Register 2 (INTSR2)

Address: 0x8000.1240, Read / Write

Definition: This register is an extension of INTSR1. This interrupt status register

also reflects the current state of the new interrupt sources within the

EP73xx. Eac h bit is set if th e appropriate interrupt is active. The

interrupt assignment is given below.

Bit Descriptions:

RSVD: Unknown during Read.

KBDINT: Keyboard interrupt. T his interrupt is generated whenever a key is

pressed, from the l ogical OR of the first 6 or all 8 o f the P ort A

inputs (depending on the state of the KBD6 bit in the SYSCON2

writing to the KBDEOI location. KBDINT is not deglitched.

SS2RX: Synchronous serial interface 2 receives FIFO half or greater full

interrup t. This is generated when RX FIFO contains 8 or more

half-words. This interrupt is cleared only when the RX FIFO is

emptied or one SSI2 clock after RX is disabled.

SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty

interrup t. This i s generated when TX FIFO contains fewer than

8 byte pairs. This interrupt gets cleared by loading the FIFO with

more data or disabling the TX. One synchronization clock is

required when disabling the TX side before it takes effect.

UTXINT 2: UART2 tran smit F IF O half empty interrupt. T h e function of this

interrup t s ource depends on whether the UART2 FIFO i s enabled.

If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate

and line control register), this interrupt will be active when there

is no data in the UART2 TX data holding register and be cleared

bywritingtotheUART2dataregister.IftheFIFOisenabled,this

interrupt will be active when the UART2 TX FIFO is half or more

empty and is cleared by filling the FIFO to at least half full. The

FIFO is 16 bytes deep.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD URXINT2 UTXINT2 RSVD SS2TX SS2RX KBDINT