User Manual

4-10 EP7309/11/12 User’s Manual - DS508UM4

Interrupt Controller

UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function

of th is interrupt source depends on whether the UA RT1 F IF O is

enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART1

bit rate and line control register), this interrupt will be active when

thereisnodataintheUART1TXdataholdingregisterandbe

cleared by writing to the UART1 data register. If th e FIFO is

enabled this interrupt will be active when the UART1 TX FIFO is

half or more empty, and is cleared by filling the FIFO to at least

half full. The FIFO is 16 bytes deep.

URXINT1: Internal UART1 receive FIFO half full interrupt. The function of

this interrupt source depen ds on whether the UART1 FIFO is

enabled. If the FIFO is disabled this interrupt will be active when

there is valid RX data in the UART1 RX data holding register and

be c leared by reading this data. If the FIFO is enabled this

interrupt will be active when the UART1 RX FIFO is half or more

full or if the FIFO is non empty an d no more characters have been

received for a three character time out period. It is cleared by

reading all the data from the RX FIFO. The FIFO is 16 bytes deep.

UMSINT: Internal UART1 modem status c hanged interrupt. This interrupt

will be active if either of the two modem status lines ( CTS or DSR)

change state. It is cleared by writing to the UMSEOI location.

SSEOTI: Synchronous serial interface end of transfer interrupt. This

interrupt will be active after a complete data transfer to and from

the external ADC has been com pleted. It is cleared by reading the

ADC data from the SYNCIO register .

Interrupt Mask Register 1 (INTMR1)

Address: 0x8000.0280, Read / Write

Definition: This interrupt mask register is a 32-bit read/write register, used to

selectively enable any of the first 16 interrupt sources within the

EP73xx. I nterrupts associated with bits 0 through 3 generate a fast

interrup t request to the ARM720T processor (FIQ) , causing a jum p

to processor virtual address 0000.001C. All other interrupts generate

a standard interrupt request (IRQ), causing a jump to processor

virtual address 0000.0018. Set the appropriate bit in this register to

enable th e corresponding interrupt. All bits are cleared by a system

reset. Consult the bit definitions for INTSR1 for information about

interrup ts associated with each mask bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SSEOTI UMSINT URXINT1 UTXINT1 TINT RTCMI TC2OI TC1OI EINT3 EINT2 EINT1 CSINT MCINT WEINT BLINT EXTFIQ