User Manual

4-8 EP7309/11/12 User’s Manual - DS508UM4

Interrupt Controller

Interrupt Register Descriptions

Interrupt Status Register 1 (INTSR1)

Address: 0x8000.0240, Read Only

Definition: The interrup t status register is a 32-bit read only register. The

interrupt status register reflects the current state of the first 16

interrupt sources within the EP73xx. Each bit is set if the appropriate

interrupt is active. The interrupt as sign men t is given below.

Bit Descriptions:

RSVD: Unknown during Read.

EXTFIQ: External fast interrupt. This interrupt will be active if th e

nEXTFIQ

input pin is forced low and is mapped to the FIQ input on the

ARM720T processor.

BLINT: Battery low i nterrupt. Th is interrupt will be active if no external

supply is present (

nEXTPWR is high) a nd the battery OK input p in

BATOK is forced low. This interrupt is de-glitched with a 16 kHz

clock, so it will only generate an interrupt if it is active for longer

than 125 µs. I t is mapped to th e FIQ input on the ARM720T

processor and is cleared by writing to th e BLEOI location. BLINT

is disabled during Th e Standby State.

WEINT: Ti ck Wa tch dog expired interrupt. This interrupt will become

active on a rising edge of the periodic 64 Hz tick interrupt clock if

the tick interrupt is still active (i.e., if a tick interrupt has not been

serviced for a complete ti ck period). It is mapped to the FIQ input

on the ARM720T processor and the TEOI location.

Note: WEINT and watchdog timer are disabled during the Standby State. The watch

dog tim er tick rate is 64 Hz (in 13 MHz and 73.728–18.432 MHz modes).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SSEOTI UMSINT URXINT1 UTXINT1 TINT RTCMI TC2OI TC1OI EINT3 EINT2 EINT1 CSINT MCINT WEINT BLINT EXTFIQ