User Manual

4-6 EP7309/11/12 User’s Manual - DS508UM4

Interrupt Controller

Interrupt Latencies in Different States

Operating State

The ARM720T processor checks for a low level on its F IQ and IRQ inputs at the end of

each instruction. The interrupt latency is therefore directly related to the amount of

time it takes to complete execution of th e current instruction when the interrupt

condition is detected. There is a one to two clock cycle synchronization penalty

following the assertion of the interrupt. For exam ple, if the EP73xx is operating at

13 MHz with a 16-bit external memory system, and instruction sequence stored in

one wait state FLASH memory, the worst-case interrupt latency is 251 clock cycles.

This delay will include:

• Instruction fetch to complete LDM r0!, (r0-r15) worst case. This is a qu ad

word quad instruction burst on the memory bus.

• Ti me for interrupt signal(data abort)

• Write Buffer flush (result of LDM instruction)

•3TLBmisses(worstcase)

•6cachemisses(worstcase)

• 1 additional cache an d MMU mi ss due to f etch from vector space

The ARM720T processor, operating at 13 MHz, has a worst-case interrupt latency of

about 19.3 ms in the example system. For those interrupt inp uts which have de-

glitching, the interrupt latency is i ncreased by the maximu m time required to p a ss

through the deglitcher, which is approximately 125 µs (2 cycles of the 16.384 kHz

clock derived from the RTC oscillator). Adding th e deglitcher creates an absolute

worst-case latency of ap proxim ately 141 ms. If the ARM720T is run at 36 MHz or

greater, the 19.3 ms value will be reduced.

All serial data transfer peripherals included in the EP73xx (except the master-only

SSI1) have local buffering to ensure a reasonable interrupt latency response

requirement for the OS of 1 ms or less. This assumes that the design data rates do not

exceed the data rates described in this specification. If the OS cannot meet this

requirement, there will be a risk of data over/unde rflow occurri ng .

Idle State

When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after

approximately two clock cycles. However, there is p otentially up to 20 ms l atency as

described above, unless the code is written to include at least two single cycle

instructions immediately after the write to th e IDLE register (in which case the

latency drops to a few microseconds).

This is important, as the I dle State c an only be l eft because of a pending interrupt,

which has to be synchronized by the processor before it can be serviced.