User Manual

EP7309/11/12 User’s Manual - DS508UM4 3-3

Timers

Prescale Mode

Any value written to TC1 or TC2 is a utomatically re-loaded when the counter

underflows. Any value written to TC1 or TC2 will be dec remented on the second

edge of the selected c lock. Setting bit 4 or 6 in SYSCON1 for TC 1 and TC2

respectively, will initiate prescale mode.

RTC Timer

The RTC timer is derived from the RTC clock. The timer interface creates a 1 Hz tick

that can be controlled by the RTCDR (RTC data register). This 32-b it read/write

next rising edge of the 1 Hz clock . Any value may be written to this register.

The interrupt driven from this c lock comes from the RTCMR (RTC Match R egister).

Once the v alue in the match register actually “matches” the value in the data register,

the interrupt will as sert.

Timer Register Descriptions

Timer Counter 1 Data Register (TC1D)

Address: 0x8000.0300, Read/Write

Definition: The timer counter 1 data register is a 16-bit read/write register

which sets and reads data to TC1. Any value written will be

decremented on the next rising edge of the clock.

Timer Counter 2 Data Register(TC2D)

Address: 0x8000.0340, Read/Write

Definition: The timer counter 2 data register is a 16-bit read/write register

which sets and reads data to TC2. Any value written will be

decremented on the next rising edge of the clock

Real Time Clock Data Register (RTCDR)

Address: 0x8000.0380, Read/Write

Definition: The Real Time Clock data r egister is a 32-bit read/write register,

which sets an d reads the binary time in the RTC. Any value w ritten

will be incremented on the next rising edge of the 1 Hz clock. This

nPOR.