User Manual

EP7309/11/12 User’s Manual - DS508UM4 2-15
Copyright Cirrus Logic, Inc. 2003
CPU Core
22
2
2. Once nPOR goes high, the EP73xx will enter Standby State. In this state, the
PLL is not enabled and thus the CPU is not turned on. The
WAKEUP signal
must be asserted
3. After
nPOR goes high, the WAKEUP signal will be detected by the processor
after one to two seconds. After suc h time, the
WAKEUP (active high) signal
can be detected but must be asserted high for a minimum of 125 µs
Note: IMPORTANT. nURESET must not be asserted during the period between
WAKEUP assertion and transition from Standby to O perating state. This will
cause t he processor to enter an unknown state and require a system reset to
clear this condition.
4. Once th e WAKEUP signal is detected internally, it first enters a deglitching
circuit which is the reason for the 125 µs duration. The PLL is then enabled
and the CPU turns on .
WAKEUP signal is then ignored and will only be
read again after a
nPOR assertion or power is cycled on the device at which
time the EP73xx will return to Standby.
WAKEUP is also ignored during
Idle state.
5. Once th e
WAKEUP signal has been detected, a maximu m of 250 m s will
elapse before the CPU i s turned on and beg ins fetching the first instruction.
RESET
There are three asynchronous resets to the EP73xx: nPOR, nPWRFL,andnURESET.If
any of these are active, a system reset is generated internally. This will reset all
internal registers in the EP73xx except the RTC data and m atch registers. These
registers are only cleared by
nPOR.
Any reset will also reset the CPU an d cause it to start execution at the reset vector
(address 0x0) w hen the EP73xx returns to the operating state.
Internal to the EP73xx, three different signals are used to reset the storage elements.
These a re
nPOR, nSYSRES,andnSTDBY.
nPOR (active low) is the highest priority reset signal and i s also the external signal
that forces the internal signals
nSYSRESandnSTDBY (equivalent to the external RUN
signal) active. nPOR will only be active after the EP73xx h as first powered up and not
during any other resets.
nPOR active w ill clear all flags in the status register except for
the cold reset flag (C LDFLG) which is bit 15 of the SYSFLG register.
nSYSRES (System Reset, active low) is g enerated internally to the EP73xx if nPOR,
nPWRFL,or nURESET are active. It is the second highest priority reset signal, used to
asynchronouslyresetmostinternalregistersintheEP73xx.
nSYSRES (when active)
forces
nSTDBY and RUN low which is the result of the CPU resetting and the EP73xx
going into Standby. T his can be done without co-operation from the system software.
The
nSTDBY and RUN signals are h igh when the EP73xx is in Operating or Idle state.
The
nSTDBY will disable an y peripheral block that is clocked from the CPU clock
except th e RTC.