User Manual
2-12 EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
CPU Core
2
internal PLL is not used. The default value “00” for the PLL setting in SYSCON3 must
not change.
CPU State Control
There are three principal power management states on the EP73xx processor
• Operating State (highest power consumption)
• Idle State
• Standby State (lowest power consumption)
Each state leaves on or turns off a unique set of CPU peripherals which can serve to
reduce or limit the power required for the system for blocks of time in which there is
no external system activity. The processor can enter or exit any one of the three states.
Standby State
Standby s tate is the low est power s tate the processor c an achieve and still be capable
of returning to operating s tate or e q u ates to th e system being switched off. Th e RTC
clock remains on to insure that the processor can “wake up” from an external
interrupt or the “wake up” signal.
When the EP 73xx is f irst powered on, the processor is in a “cold reset”. The sam e
condition can be created by asserting
nPOR. Cold reset for the processor is the
standby state. In this instance, none of the peripherals have been initialized so the
only method for e ntering the oper ating state is by means of the
WAKEUP pin.
Clock Status
• If internal PLL is used, it will s hut off
• If external 13 MHz clock is being used, CPU will ignore i nput. External
Figure 2-4. State Diagram
Standby Operating
Idle
Interrupt or rising wakeup
Write to standby location,
power fail, or user reset
I
n
t
e
r
r
u
p
t
Write to halt location
nPOR, power fail,
or user reset